CAST Adds Multicast and AXI to UDP/IP Core for Streaming Media Systems
Woodcliff Lake, NJ, February 19, 2013 — Semiconductor intellectual property provider CAST, Inc. has improved its UDP/IP Hardware Stack IP core with customer-requested features that make it even more effective for processor-less streaming of audio or video over Ethernet.
The User Datagram Protocol (UDP) is a transport layer communications standard within the Internet Protocol suite that is simpler and quicker than Transmission Control Protocol (TCP/IP). This makes it better for video or audio media streaming over the Internet or within a private network; the GigE Vision, ONVIF, and PSIA standards for IP-based cameras, for example, all incorporate UDP.
CAST’s hardware UDP stack core handles the millions of instructions per second that a host processor would otherwise spend on UDP framing and checksum validation. The new version supports IP multicast for delivery of a single source’s data to multiple receivers using the IGMPv3 standard, and it adds an interface to the AMBA® AXI4 bus for easier integration of UDP in high-performance systems.
“Our UDP stack core is one of the smallest available,” said Tony Sousek, an IP development manager at CAST. “Now with IP multicast and AXI4 bus support, the UDPIP partners perfectly with our compression codecs and Ethernet MACs to more efficiently handle streaming media for Internet television and other popular applications.”
The improved UDP/IP Hardware Core Stack is available now, alone or integrated with an Ethernet MAC core from CAST, Altera, or Xilinx or with any of CAST’s video and image compression cores. Call CAST at +1 201.391.8300 or visit www.cast-inc.com for more information.
|
CAST, Inc. Hot IP
Related News
- CAST Full Hardware UDP/IP Stack Core Simplifies Streaming Media Over IP Networks
- TCP/IP Hardware Stack IP Core now Available from CAST
- CAST Expands Popular UDP/IP Networking Cores Line
- Digital Blocks Announces 2nd Gen Audio/Video & Data Hardware Protocol Stacks Supporting MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols
- Digital Blocks Releases 2nd Gen UDP/IP Hardware Stack / UDP/IP Off-Load Engine (UOE) Targeting High-Frequency Trading Systems
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |