Bytom -- March 8, 2013
-- The DμART is a soft core of a Universal Asynchronous Receiv-er/Transmitter (UART). It can perform both, serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the CPU. The CPU itself can read the complete status of the UART at any time during the func-tional operation. Reported status information includes the type and condition of the transfer opera-tions being performed by the UART, as well as any error conditions, like overrun or framing.
The DμART includes also a programmable baud rate generator – says Jacek Hanke, CEO at Digital Core Design - which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock, for driving the internal transmitter logic. Provisions are also included to use this 16 × clock, to drive the receiver logic. The newest UART Core from Digital Core Design has been also equipped with a processor-interrupt system. Thanks to it, the interrupts can be pro-grammed according to the user's requirements, minimizing the computing required to handle the communications link.
The DμART core is perfect for applications, where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. DCD’s solution is also suitable for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices as well.
More information & data sheet: http://dcd.pl/ipcore/690/duart/
- Majority Voting Logic
- Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
- In a UART mode, receiver and transmitter are double buffered, to eliminate the need for precise synchronization between the CPU and serial data
- Independently controlled transmit, receive, line status, and data set interrupts
- 16 bit programmable baud generator
- False start bit detection
- Line break generation and detection. Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Overrun, framing error detection
- Full prioritized interrupt system controls
- Technology independent HDL Source Code
- Fully synthesizable static design with no internal tri-state buffers