OCP-IP Releases OCP Debug Socket Specification 2.0
BEAVERTON, Ore., Mar 26, 2013 -- Open Core Protocol International Partnership (OCP-IP) has released the OCP Debug Socket Specification 2.0. The latest version now includes support for Low Power Signaling as well as Cache Coherence signals that are available in the current version of the OCP specification. This allows the most complex processors to be debugged with exact visibility of traffic to or from the OCP bus on all levels of transactions, including all transfer states.
The additional debug signal interface definitions provided by the OCP Debug Socket Specification 2.0 ensure OCP remains the most complete and advanced multicore SoC socket available today. It addresses the visibility and control needed to best analyze the operation of OCP architectures and their design flows and provides a common set of debug options with consistent signal interfaces.
"With the evolution of heterogeneous Multi-Core Systems On the Chip (MC-SoC) the debug interconnection deserves special attention," said Ian Mackintosh, President of OCP-IP. "A set of standardized signaling and definitions make the debug wiring core-independent to match the OCP standard, and in doing so stimulates the development of predefined and verified debug IP blocks for quick and successful assembly of large MC-SoCs."
For a copy of the OCP-IP Debug spec version 2.0 click here.
Non-Members may access their copy by completing the Research License Agreement.
For all the latest information on OCP-IP please see our latest newsletter at: www.ocpip.org/newsletters.php.
About OCP-IP
Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.
|
Related News
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |