True 32 Million-Gate capacity Hammer Hardware Accelerator sets a new price/performance standard while offering the much needed verification platform for complex system-level designs
Santa Clara, Calif -- May 13, 2002 --Tharas Systems, Inc., a provider of a new generation of hardware acceleration solutions, today announced that its second-generation Hammer (TM), a true 32 Million RTL gate equivalent capacity hardware accelerator is currently in Beta and first customer shipment is slated for June 3, 2002. The new Hammer will be available in 8, 16 and 32 Million RTL gate configurations.
"The industry is looking for hardware-assisted verification solutions, especially at the system-level. For instance an OC192 line card can be anywhere from 10 to 15 Million gates. What is enticing to our customers is the fact that they now can verify interactions between multiple line cards in a reasonable time, prior to committing the ASICs for fabrication. The addition of these new configurations at compelling price/performance points will advance widespread usage of RTL hardware acceleration both at the System and ASIC level," says Prabhu Goel, Chairman & CEO of Tharas Systems.
Hammer 32M is priced at US$780,000 for a 32 Million RTL gate-equivalent and 4 Giga Bytes of memory capacity, while Hammer 16M which is capable of accelerating 16 Million RTL gate-equivalent and 2 Giga Bytes of memory design is priced at US$480,000. Tharas Systems will continue to offer the current 2M, 4M and 8M – 2, 4 and 8 Million RTL gate-equivalent configurations respectively.
"For complex system verification, the traditional approach of deploying software simulators just doesn't cut it. FPGA-based acceleration and emulation is plagued by painfully long compile times, reduced visibility during debug and more importantly the unavailability of system and software ready to drive real-world signals, prior to ASIC sign off. Hammer offers fast compile and run times with ease of use comparable to that of software simulators. Run times range from 10 to 1000 times faster than software simulators. FPGA-based acceleration systems have severe capacity limitations due to issues with partitioning and utilization among FPGA devices. The attractively priced Hammer 32M and Hammer 16M is setting a new price/performance yardstick in the industry," notes Rahm Shastry, Senior Vice President of Marketing & Sales at Tharas Systems.
Tharas Systems' Hammer provides Verilog simulations with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Compile times are as fast as 10 Million RTL gate-equivalent per hour as compared to 8 hours per Million RTL gate-equivalent for other FPGA-based systems. Run times range from 10 to 1000 times faster than software simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug – contrast this to dramatic loss of performance during run time of competing FPGA-based systems during debug.
Hammer works with existing RTL and gate-level verification environment. As a result, designers can continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ: SNPS) and Cadence Design Systems, Inc. (NYSE: CDN).
Hammer supports design sizes of 32 Million gate-equivalent RTL code, and can be combined with multiple memory models up to 4 Gigabyte in hardware. Hammer pricing ranges from US$115,000 to US$780,000.
About Tharas Systems
Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/. For more specific product information, email email@example.com or call 1-408-855-3200
Note to editors:
Hammer is a registered trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.