LG Adopts In-Design Physical Verification with IC Compiler and IC Validator after Multiple Successful Tapeouts
Synopsys IC Validator Enables LG Electronics to Accelerate Manufacturing Compliance
MOUNTAIN VIEW, Calif., April 15, 2013 -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that LG Electronics, Inc. has adopted IC Validator, Synopsys' physical verification applications tool, as part of their design implementation flow for ARM® processors. Key to LG Electronics' adoption was IC Validator's In-Design technology integration with Synopsys' IC Compiler™ place-and-route solution. In contrast to the older iterative approach of physical design followed by verification, the In-Design approach accelerated manufacturing compliance for LG Electronics by two weeks.
"Competitive implementation of ARM processors in our designs is critical to market leadership and drives our platform strategy," said Dr. Woo-Hyun Paik, Research Fellow of SIC R&D Lab, at LG Electronics. "We found IC Validator's In-Design approach to physical verification crucial to ensuring manufacturing compliance while honoring the performance, power and other constraints of complex, high-performance, energy-efficient processor design. In our recent tapeouts, we have successfully used key IC Validator capabilities, including timing-aware fill and automatic design rule checks (DRC) repair, enabling us to achieve manufacturing compliance ahead of schedule."
With feature geometries shrinking, the number and complexity of DRC needed to achieve manufacturing compliance has grown exponentially. This has rendered the traditional physical verification approach, which relies on modifications to design after the GDSII has been generated, disadvantageous. The traditional approach can create multiple discover-then-fix iterations and can lead to suboptimal results. Examples are metal-fill insertion and design-rule checking, which today are universally mandated manufacturability compliance steps. The traditional approach would require physical designers to stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any errors, setting the stage for multiple iterations. The same concerns are also applicable to the traditional approach to generalized design rule checking after the design has been completed, potentially leading to late-stage surprises and ensuing expensive iterations that can significantly impact tapeout schedules.
In-Design physical verification with IC Validator addresses these manufacturability challenges within the IC Compiler environment. The well-integrated flow enables an optimized metal-fill flow that is not only timing aware with sign-off quality, but also avoids expensive and error prone stream-outs and stream-ins. For design rule checking, the In-Design flow uses foundry-qualified rule decks to flag errors in the layout and also drive automated repair, potentially saving days compared to the traditional approach of post-design validation and subsequent manual repairs.
"In-Design physical verification with IC Compiler and IC Validator exemplifies how smart technology integration of the right platforms offers a high-efficiency turnkey solution to enable designers to accelerate time to tapeout," said Antun Domic, senior vice president and general manager of Synopsys' implementation group. "By adopting In-Design physical verification with IC Compiler and IC Validator, LG Electronics is taking advantage of Synopsys' platform integration that offers the optimal solution for high-performance, energy-efficient ARM processor implementation."
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- UMC Adopts Synopsys IC Validator for Pattern Matching-Based Lithography Hot-Spot Verification at 28 nm
- Breakthrough Synopsys IC Validator Technologies Deliver Faster Physical Signoff Convergence
- Synopsys IC Validator Certified by Samsung Foundry for 7nm Signoff Physical Verification
- Synopsys IC Validator Certified by GLOBALFOUNDRIES for Signoff Physical Verification
- Synopsys' IC Validator Used for Physical Sign-Off on More Than 100 FinFET Production Tapeouts
Breaking News
- MIPI Alliance Announces OEM, Expanded Ecosystem Support for MIPI A-PHY Automotive SerDes Specification
- Deeptech Keysom completes a €4M fundraising and deploys the first “no-code” tool dedicated to the design of tailor-made processors
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Faraday and Kiwimoore Succeed in 2.5D Packaging Project for Mass Production
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
Most Popular
- RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Electronic System Design Industry Posts $4.7 Billion in Revenue in Q2 2024, ESD Alliance Reports
- Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024
- OPENEDGES Technology Achieves ISO 26262 ASIL-B Certification
E-mail This Article | Printer-Friendly Page |