Enables design teams to reduce the cost and risk of verification of power-domain partitioned SOCs
May 14, 2013, MOUNTAIN VIEW, Calif. — Jasper Design Automation, the leading provider of verification solutions based on state-of-the-art formal technology, has announced the availability of its new JasperGold® Low Power Verification App (JG-LPV App) which enables users to utilize formal methods for the verification of SOC designs optimized for lower power consumption with multiple voltage and power-management domains. The JG-LPV App reads the RTL description and creates an internal power-aware formal model in accordance with the power partitioning specifications. The new App verifies power optimization structures, power management circuitry, power sequencing, and works with other JasperGold Apps to verify that the power optimizations do not corrupt the original design functionality. The JG-LPV App supports the standard UPF and CPF power intent specification formats. The App’s automated approach, together with the exhaustive nature of formal verification, can reduce verification time, cost, and risk compared to traditional power-aware verification approaches.
While many tools and methodologies are used for power estimation, power optimization and structural verification, JG-LPV is designed specifically to verify the correct implementation of the power intent specification and the functionality of the design after the insertion of power management circuitry. Its automation makes it critical in the verification of SOC designs, in which low-power management constructs are introduced at different phases in the SOC development, depending upon the data available and the optimizations required. The App’s automation can significantly reduce the design time, cost, and risk of this complex, iterative process, compared with traditional approaches such as spreadsheet analysis, automated structural analysis, manual functional analysis, power-aware simulation, and power-related design rule checking (DRC).
“Reducing power consumption has become mission-critical for most chip designers today, whether the SOCs are in mobile appliances with limited battery life or in big-box electronics where excessive power consumption and excessive heat generation are not permissible,” said Lawrence Loh, Vice President of Applications Engineering, Jasper Design Automation. “The exhaustive nature of JG-LPV’s formal verification yields a quality of results superior to those of power-aware simulation, which generally applies only a restricted subset of directed tests to the design. JG-LPV also assures the correctness of the design after the insertion of power management circuitry, in contrast to approaches such as structural analysis, which assures only consistency between the RTL and the power intent specification. The new App helps to reduce our customers’ effort, cost and risk associated with verifying the overall functionality of power-optimized designs.”
JasperGold Low Power Verification App
The Low Power Verification App uses the power intent specifications to automatically generate an internal power-aware RTL model that is an accurate representation of the power domain specifications. The new App also inserts power supply network, switches, isolation cells, and data retention cells into the internal model. The App then extracts power sequencing information from the power specification file(s) and infers a sequence of power control events that must take place in order to implement the power up/down correctly.
The App also tests the power control sequences — with arbitrary time steps — and performs formal analysis to assure that the power sequences are correct and consistent. The states that are reached at the end of the sequences, and the inferred power-optimized RTL, are also used to perform proofs to verify that the chip functionality is not corrupted.
JG-LPV can also leverage other JasperGold Apps to verify that power domains and power management circuitry throughout the design do not corrupt the intended function of the design.
About JasperGold Apps
JasperGold Apps are built on a single platform that combines multiple formal-based solutions and leverages a common shared database and user interface. The Apps architecture enables sharing of design and verification data for each design under test (DUT) between Apps for increased consistency and productivity. The Apps architecture supports deployment of multiple Apps simultaneously as well as multiple invocations of the same App for improved throughput and performance.
The Apps architecture is extensible such that customers can take advantage of future Apps that will address emerging design and verification needs. The design and verification challenges that customers have addressed by creating flows using our formal technology have been the inspiration for several Apps. Customers will be able to continue to leverage the powerful and highly programmable platform in JasperGold to develop their customized flows.
The new Low Power App is available now. For pricing and sales inquiries, please contact mailto:firstname.lastname@example.org.
About Jasper Design Automation
Jasper Design Automation delivers industry-leading software solutions for semiconductor design, verification, and Intellectual Property (IP) reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in the wireless, consumer, computing, and networking electronics industries. Jasper technology has been an essential part of 150 plus successful chip deployments. Headquartered in Mountain View, California, the company is privately held, with offices and distributors in North America, South America, Europe, Israel, and Asia. Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity and accelerate time to market.