Target Compiler Technologies Expands Architectural Exploration into IP Subsystem Design

50th Design Automation Conference – Austin, Texas, June 3, 2013. Target Compiler Technologies, a leading provider of software tools for the design of processor-laden SoCs, today announced a collection of enhancements and additions to its product line which collectively move the company firmly into the intellectual property (IP) subsystem domain.

Key among these additions is broad support for both multicore and multithreaded architectures. As the functionality and complexity of IP subsystems increase, the need to take advantage of new levels of parallelism also increases. Target’s tools already provided support for instruction-level and data-level parallelism. Functional, task-level parallelism is the next level in the design hierarchy, and this is delivered by multicore and multithreaded architectures. Increasing subsystem parallelism with such architectures keeps design teams on target with respect to needed improvements in performance and power efficiency.

The announcement comes with three key components:

First is Target’s new MP Designer™ product. After a successful beta program, Target is now announcing general availability for MP Designer. MP Designer is a tool-suite that helps engineers balance both software and hardware decisions for multicore subsystems. With MP Designer, engineers can quickly explore software parallelization and hardware architecture options in search for optimal solutions. Its patented approach turns the tables on multicore software development by working directly off of sequential C code, generating parallel implementations, and guaranteeing correctness. MP Designer includes an intuitive and integrated multicore debugger, simplifying software debug for complex, parallelized applications.

Second is an increase in architectural breadth of Target’s IP Designer™ tool-suite for the design of application-specific processors (ASIPs). Customers can now model multi-threaded architectures. Architectural solutions supported include preemptive multithreading schemes with infrequent context switching suited for low-power systems, as well as advanced barrel processors with interleaved multithreading.

Third is a significant increase in scope in IP Designer’s modeling capability. Next to the instruction-set architecture, designers can now model advanced communication and memory interfaces for their ASIPs. Typical examples include bus interfaces, memory banks, and cached memories. IP Designer automatically generates the hardware implementation of such interfaces, as well as a simulation model enabling virtual prototyping of the ASIP in its subsystem.

“While the IP Designer tool-suite addresses the design and optimization of individual ASIP architectures, we have long found that IP Designer customers are trying to fit such ASIP cores into larger IP subsystems,” commented Dirk Lanneer, co-founder and vice-president of tool development at Target. “We therefore saw a growing need for tools to support multicore, multithreading, and communication design aspects at large. With our new capabilities, customers can enjoy unprecedented levels of performance and power efficiency in highly flexible acceleration subsystems,” Lanneer added.

“We believe that architectural exploration is a key need in our industry,” said Gert Goossens, co-founder and CEO of Target. “And, the enabler for architectural exploration is rapid and accurate generation of variant implementations according to high-level tradeoffs. Architectural exploration of instruction-set architectures is what IP Designer has been built for from day one. With today’s announcements, we make a significant step towards extending architectural exploration to the level of IP subsystems in system-on-chip design,” Goossens said.

MP Designer and these extensions to IP Designer are available today from Target Compiler Technologies. The products are provided under an EDA software licensing model and carry no royalties tied to the IP developed.

About Target Compiler Technologies

Target Compiler Technologies offers software tools for the design of advanced multicore systems-on-a-chip (SoCs). Target’s IP Designer™ product is the leading tool-suite that enables and accelerates the design, programming and verification of application-specific processor cores (ASIPs). Target’s MP Designer™ product is a tool-suite for software parallelization on multicore SoC architectures. These tools are ideally suited for SoC designs in markets that mandate low silicon cost, low energy consumption, and flexibility to accommodate post-manufacturing changes. Target’s tools have been used by customers around the globe to design SoCs for wireless systems (e.g. 3G/4G handsets, access points, VOIP phones), audio/video/image/graphics processing, automotive systems, industrial control, security, network infrastructure, hearing instruments, and personal healthcare systems. Target is a spin-off of IMEC, is headquartered in Leuven, Belgium, with North American operations in Boulder, Colorado. For more information, visit http://www.retarget.com.