June software release features new high-performance Ethernet packet processing solutions
SANTA CLARA, Calif., June 4, 2013 – Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, today announced the availability revision 2.6.2 of its Stylus compiler, which supports its ABAX2P1 device and its suite of high-performance Ethernet packet processing solutions. This release marks a new step in Tabula’s ongoing software roadmap execution. It delivers new unique capabilities including a 100G Ethernet packet parser reference design, enhanced ECC support, and 30% reduction in runtime. Stylus revision 2.6.2 is available now for download on tabula.com, at no-charge to customers.
New features and additional design kits included with this release
- Reference design: Configurable 100G Ethernet packet parser
- The new 100GbE packet parser represents a novel approach to this class of network functions, delivering a unique combination of programmability and low latency currently not achievable on a programmable device. For more information on the 100GbE packet parser Reference Design Kit: www.tabula.com/news/read_more.php?id=29
- Design example: 8 MB/2 GHz buffer with ECC
- Enhanced support for user-RAM ECC
- In excess of 200 new features and usability improvements that continue to make high-performance design easy
More about the Stylus compiler
Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture, unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. It integrates cutting-edge timing closure technologies including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-ported memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.
Stylus revision 2.6.2 and the 100G Ethernet Packet Parser Reference Design Kit are available now and free of charge.
Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs), based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com