SUNNYVALE, Calif. With a promise that users will be able to create custom communications chips within a few minutes, QuickLogic Corp. this week will roll out WebESP, a Web-based design system based on preconfigured intellectual-property (IP) blocks. The system will allow users to select, configure and combine parameterized functions and receive product samples in as little as one day, the company said.
WebESP is aimed at a narrow applications space communications bridging chips. Initial support is for Utopia I, II and III interfaces, with POS-PHY and CSIX functions to be added within a few weeks. QuickLogic will also provide PCI functions.
"We found there are applications where the set of functions can be fairly well-constrained and known ahead of time," said Chuck Tralka, director of marketing for interconnect solutions at QuickLogic. "It isn't necessary to go through the standard tool flow to complete that kind of design."
To create WebESP, Tralka said QuickLogic built up a library of IP with a common interface such that IP functions can work together. The IP can be mapped to any silicon platform QuickLogic provides. In fact, users don't choose the platform that's all handled by QuickLogic, depending on the design requirements.
QuickLogic is best known for its ESP devices, which combine FPGA logic with embedded functions. The standard tool flow, embodied in the vendor's QuickWorks offering, includes schematic capture, HDL synthesis, simulation, timing analysis and compilation.
With WebESP, designers can set all that aside and simply fill out a menu of options for the chosen application. That's possible because the underlying IP has already been synthesized, verified and laid out. QuickLogic then programs sample chips for delivery to the customer.
Compilation is transparent to the user. "For the first set of functions, we've already pre-completed all of the designs," said Tralka. "We may ultimately do real-time placement and routing, but it's not there yet."
There are, however, some trade-offs. "With the standard QuickWorks flow, you can create anything within the capabilities of the device, and you also have much greater control over utilization and performance," Tralka said. "With WebESP, you're giving up any function we don't support, and you're giving up a degree of flexibility for each of the supported functions."
WebESP, Tralka said, is "a way to get a more flexible standard product rather than a true ASIC or FPGA alternative." QuickLogic uses the term "customizable standard product" to describe the output of WebESP.
WebESP is accessed from www.quicklogic.com/webesp. Users first choose an application, such as a Utopia master bridge. They can pull up a text description and a block diagram that describes what the function does.
Then, users fill out a list of options. For a Utopia master bridge, they select the type and level, bus width and package. Options such as bus speed, status indication, cell size, transfer mode and parity are not selectable in this case, but they may be for other types of devices.
After filling out the list, users get a configuration summary and a parts number. WebESP generates a detailed data sheet for the part configuration. Users then fill out shipping information and provide some project information. QuickLogic returns the samples, and the user can run some verification and decide whether to purchase the part for production purposes.
At the outset, WebESP is free, although QuickLogic says it may charge for it later.
"The intention is to create opportunities for production orders," said Tralka. "We don't charge for the silicon we ship as prototypes. We don't even charge for the shipping."