PCIe takes on mobile, Thunderbolt, more
Rick Merritt, EETimes
6/26/2013 8:00 AM EDT
SANTA CLARA, Calif. – The spec is done for a mobile interconnect that will pack PCI Express into smartphones and tablets. Cadence and Synopsys showed working silicon for the M-PCIe interface at the annual meeting of the PCI Special Interest Group here.
The spec lets PCIe protocols ride the M-PHY defined by the MIPI trade group and already widely used in mobile devices. OEMs will adopt the interface to lower costs and shrink development times by reusing PCIe software to replace a wide variety of mobile interconnect protocols.
Separately, the PCI SIG expects to finish work before June 2014 on OcuLink, a 32 Gbit/second cabled version of PCIe. It aims to deliver more bandwidth than the rival Thunderbolt interconnect backed by Apple and Intel at “orders of magnitude lower cost,” said Ramin Neshanti, marketing workgroup chair of the PCI SIG.
In addition, the group announced progress on its Gen 4.0 spec, expected to be the last turn of the crank for copper in pcb interconnects. It will support 16 GTransfers/second and be complete in early 2016.
The SIG also detailed a handful of enhancements to the 8GT/s Gen 3 spec and a new form factor for mobile devices called M.2 that aims to replace mini-PCIe cards.
The M-PCIe news took center stage at the event. It is expected to appear in apps processors, Wi-Fi combo devices, bridge chips and storage controllers. First SoCs using it could tape out early next year, said a Cadence product manager.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
- Arm takes centre stage at Mobile World Congress 2019
- Synopsys Releases Verification IP for Mobile PCIe Technology
- PCI-SIG and MIPI Alliance Announce Mobile PCIe (M-PCIe) Specification
- PCI-SIG and MIPI Alliance Collaborate to Extend PCI Express Technology to Mobile Devices
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation