July software release features new high-performance search reference designs and IP cores
SANTA CLARA, Calif., July 2, 2013 – Continuing its momentum in innovating how programmable devices are applied to network infrastructure systems, Tabula, Inc. announced today the availability of version 2.7 of its Stylus® compiler supporting its ABAX®2 P-Series of 3D programmable logic devices (3PLDs). Stylus 2.7 is a critical milestone in Tabula’s ongoing software roadmap to provide customers with comprehensive high-performance Ethernet packet processing solutions. To help accelerate the development of high-performance applications, the software features new tool enhancements with unique capabilities, including 100G Ethernet search IP cores, enhanced FIFO support, and a comprehensive design power analysis suite.
The new capabilities and design kits introduced in the Stylus 2.7 release include:
- Soft IP cores: A high-performance 100 GbE search IP kit composed of ternary search engines, including both associative and exact-match cores (second generation). Developed in collaboration with Algo-Logic Systems, a leader in search IP, these cores deliver 150 million packets per second (MSPS) at a 100G line rate with a low, deterministic latency of 256 ns. For more information on the 100G search IP kit, visit https://www.tabula.com/news/read_more.php?id=32
- Reference design: A 12 × 10G-to-100G Ethernet bridge (version 2.0) supporting 100 GbE traffic without packet drops, utilizing a deficit-weighted round-robin arbiter, which allows priority assignments of each 10 GbE port.
- Design examples: A 24-bit CRC generator operating at 2 GHz, supporting a data rate of 128 Gbps.
- Design power analysis suite: A web-based pre- RTL power calculation tool that allows designers to quickly explore the power envelope of various architectural options before starting the actual design. The post-RTL calculator integrated into Stylus uses post-placement design data to track power consumption as the design evolves.
- Added capabilities: In excess of 250 new features (and improvements to usability) contribute to Tabula’s objective to make high-performance design easy.
More about Stylus compiler
Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime® architecture, unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.
Stylus version 2.7 is available now for download at http://customer.tabula.com at no-charge.
Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com