Silicon Logic Engineering Launches ASICBlaster Chip Design Services Solution to Facilitate Semiconductor Industry Ramp-Up
Engineering Expertise, Methodologies, IP, and Tools Address Outsourcing Requirements of High-End Computing and Networking Systems Companies
EAU CLAIRE, Wis. - May 20, 2002 - Silicon Logic Engineering (SLE), a provider of high-end digital application specific integrated circuit (ASIC) and system-on-chip (SOC) design services, today announced the availability of the SLE ASICBlaster™ solution that has been used to design and deliver more than 30 right-first-time chips to leading computer and networking systems customers. The SLE ASICBlaster solution leverages the vast expertise of SLE's team of seasoned chip designers who have developed and deployed highly efficient design processes and methodologies for delivering customer designs on time and within budget. The solution also utilizes internally developed software tools and semiconductor intellectual property (SIP). The complete ASICBlaster solution addresses the requirements of electronic systems design companies who embrace the growing industry trend toward chip design outsourcing as a fundamental practice to improve time-to-revenue for leading edge products.
"As the semiconductor industry moves toward positive growth again, outsourced design services will become invaluable to electronics companies who need to ramp up their design throughput," said Jordan Selburn, Principal Analyst at research firm iSupply. "The combination of expert design services, methodologies, SIP, and tools is ideal for systems design companies who do not have in-house chip design expertise or who must supplement the skills of internal teams."
Solution Leverages Team Experience
With roots in the supercomputer industry, the SLE engineering team has applied its extensive chip and high-end systems design experience to the development and subsequent deployment of the SLE ASICBlaster solution. The team's specific expertise includes:
Right-First-Time Design Track Record
- Architectural definitions and specifications
- System level electrical design and analysis
- All aspects of chip design from RTL code generation (Verilog and VHDL) through foundry hand-off including behavioral design, logic synthesis, design-for-test (DFT), timing analysis, floorplanning, high-speed interface design, clock design, and placement/routing
Working closely with many of the world's most prominent electronics systems companies, the SLE engineering team has deployed the SLE ASICBlaster solution to deliver more than 30 high gate count, high-performance ASICs and SOCs without the need for costly "respins" that are common to complex chip designs. A typical SLE ASIC contains upwards of 7 million gates and multiple clock domains.
"We are very pleased to be able to offer the result of our many years of experience delivering complex, right-first-time chip designs as a structured solution," said Jeff West, President and Founder of SLE. "Our leading-edge systems customers have come to rely on the comprehensiveness of the ASICBlaster solution, which is a combination of expertise, processes, tools, and IP blocks, to help them get their products to market faster."
SLE-Developed EDA Tools and SIP Support ASICBlaster Solution
In addition to expert design services, the SLE ASICBlaster solution makes use of internally developed software tools and SIP blocks that speed design completion and ensure accuracy. Designed to augment commercially available offerings with specific high-performance ASIC and SOC functionality, the SLE ASICBlaster software tool suite includes:
- ScanBlaster™ scan insertion utility
- DelayBlaster™ timing optimization tool
When required, SLE's ASICBlaster solution may also include licensable SIP cores. Unlike commodity SIP, the ASICBlaster cores are considered by SLE's customers to be of high value because they add clear functional differentiation and are specifically targeted toward high speed, leading edge, complex designs. Currently available ASICBlaster SIP cores include:
- High speed networking interfaces such as SPI-4 Phase 2
- Industry standard computing interfaces such as PCI2.2
- An extensive list of IEEE-compliant floating point cores
- Encryption cores such as the 3-DES Encryption Engine
SLE's ASICBlaster solution is available now for deployment on new customer designs. Design services and SIP cores may be obtained separately. The ASICBlaster tools are not available for purchase but are utilized by the SLE engineering team to complete customer designs. Specific design project engagement information can be obtained by contacting SLE's sales group.
SLE is a semiconductor design services company that provides ASIC and system technology services to the world's leading electronic systems and fabless semiconductor companies who require high-end chip design expertise. SLE's ASICBlaster solution dramatically reduces the time it takes its customers to get their products to market by offering a proven and repeatable design process, tools, and semiconductor intellectual property (SIP). Founded in 1996 by former Cray Research engineers, SLE is headquartered in Eau Claire, Wisconsin.