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Oasys Announces New Funding Led by Intel Capital, Xilinx and former Cadence CEO Joe Costello

July 25, 1013 - Oasys Design Systems announced they have raised a new round of funding led by Intel Capital, Xilinx and former Cadence CEO, Joe Costello. Funds will be used to expand the companyâ€™s sales, marketing and product development activities

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GUC Monthly Sales Report - March 2025 (April 8, 2025)
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RISC-V in Space Workshop 2025 in Gothenburg (March 31, 2025)
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RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027 (May 12, 2025)
Faraday Adds QuickLogic eFPGA to FlashKit-22RRAM SoC for IoT Edge (April 28, 2025)
Premier ASIC and SoC Design Partner Rebrands as Aion Silicon (April 28, 2025)
Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC's A16 and N2P Process Technologies (April 24, 2025)
TSMC Unveils Next-Generation A14 Process at North America Technology Symposium (April 24, 2025)