Digital Core Design Introduces 80390 CPU

August 1st, 2013 -- Digital Core Design, IP Core provider and System-on-Chip design house has introduced the DP80390 soft IP Core, which is 100% binary compatible with 8051 and 80390 instruction sets. It’s pipelined RISC architecture executes up to 200 million instructions per second and consumes just 8120 gates. Furthermore, the DP80390 is a technology independent IP Core, so it can be easily implemented in both ASIC and FPGA.

The DP80390 is a high performance, speed optimized soft core of a single-chip 8-bit embedded controller intended to operate with fast (typically on-chip) and slow (off-chip) memories. It supports up to 8 MB of linear code space and 16 MB of linear data space. – We’ve designed this IP Core with a special concern about performance to power consumption ratio – explains Piotr Kandora, R&D Director at Digital Core Design – and this ratio can be extended by an advanced power management unit (PMU).
As it’s been stated above, the DP80390 soft core is 100% binary compatible both with 80390 and 8051 instruction set. One can easily choose from two configurations:

Von Neumann, with common program and external data bus
Harvard, where internal data and program buses are separated.

The pipelined RISC architecture of the DP80390 executes 85 – 200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. - This performance can also be exploited in low power applications – adds Kandora - where the core can be clocked over ten times slower than the original implementation, without performance depletion.
The DP80390 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD's 80390 Cores has built in support for the DCD’s Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip. And unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

More information about the DP80390 is available at http://www.dcd.pl/ipcore/110/dp80390/

More information about DCD’s hardware debugger for DP80390: http://www.dcd.pl/page/154/docd/