Rick Merritt, EETimes
8/13/2013 08:03 PM EDT
SAN JOSE, Calif. — Micron's Hybrid Memory Cube -- a 4 GByte stack of DRAM die on a 160 GByte/second interface now sampling to a few close partners -- almost didn't happen. The first prototype failed to make connections between the DRAM stack and a controller inside the package, forcing an all-hands-on-deck effort to save the project.
Two top engineering managers leading the program told some of the story behind the Cube in an interview with EE Times. They also shared a few of their goals for the next-generation chip now in the works -- an 8 GByte stack transferring data at up to 320 GBytes/second with even greater power efficiency that the current samples.
The Cube got its start in early 2006 when the industry was buzzing with talk both about multicore processors and 3D chip stacks using through silicon vias (TSVs).
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