SERTEST From iRoC Offers SER Qualification For ICs
SANTA CLARA, Calif. -- May 28, 2002 -- iRoC Technologies, a leader in the field of Infrastructure IP announced SERTEST™, a new bundle of professional services for Soft Error Rate (SER) simulation, radiation testing and technology characterization of all VDSM ICs. SERTEST enables semiconductor manufacturers, system houses, fabless companies and IP providers to qualify their product with respect to an acceptable SER to assure the highest system reliability, availability and security. SERTEST saves test costs and test time by increasing flexibility and reducing test engineering steps and simulation calculations while providing an accurate SER of CMOS chips. SERTEST is easily customized to accept a broad range of different semiconductor devices as well as any technology process. Currently SER evaluation and qualification is a bottleneck due to both simulation and radiation tests because of tester stringent constraints set by beam facilities. iRoC provides a specific probe IP associated with a SEU simulator to speed-up simulation and an innovative programmable-based tester to avoid crippling PCB development for cosmic rays tests. SERTEST features the capability to merge SER evaluation and qualification into reliability test procedures without increasing the critical path length.
iRoC is the first to offer a commercial SER qualification service integrating front-end simulation and customized radiation tests. Users will now be able to meet these important goals:
- Provide a SER evaluation during the design process so that the threat of an expensive redesign is avoided.
- Qualify dies with respect to SER in a timeframe coordinated with mass production constraints.
"SERTEST provides a risk assessment value in the critical phase of IC Robustness verification through simulation at the front-end level and a SER qualification at sea level through customized radiation tests," said Eric Dupont, president and CEO of iRoC Technologies. "iRoC is the first company to bridge the gap between single event effect issue and IC mass production for commodity products."
Multiple factors can create an error that will crash a system or provide false information at a strategic point of the system electronics. Therefore, it is critically important to include a SER reliability metric as part of IC specifications and tests by system houses and chip suppliers to assure their dies provide the appropriate Failure In Time (FIT) rate. Radiation testing encompasses alpha particles and neutrons that are the two main causes of soft errors at sea level for the current technologies.
SER Expertise At iRoC
- One stop-shop for SER qualification. iRoC offers a full range of services and products to achieve a SER guarantee from technology characterization to chip SER.
- Simulation capabilities through SEUPROBE IP and ROBAN. SEUPROBE provides the critical charge and the pulse width data while ROBAN provides logic network sensitivity versus clock frequency.
- SER evaluation in the minimum timeframe. From a given die to SER evaluation report, the average time is 2 months.
- Flexible and powerful test equipment. SERTEST radiation equipment is based on SMARTESTBED, a programmable-based tester designed to meet high-end chip constraints: high speed, high number of I/Os and a broad range of DUT.
SERTEST Applicable To Memory, Logic ICs and SoC
While memories are the first devices to be attacked, designers still need to protect logic parts where high frequencies and shortened gate transition time foster the propagation of transient pulses through a logic network. Hence, the CPU and SoC need to be tested as well. SERTEST offers in this first version the capability to test memories and CPUs. In the future it will test any kind of SoC.
The iRoC IC Protection Solution Approach
SERTEST is only one in a growing family of products and services for Robustness from iRoC.
Risk Assessment is the first of three phases to bring fully protected circuits to market. In this phase the goal is to get a SER approach to establish the right protection strategy. The more data made available, the more accurate the assessment will be. Technology characterization will provide the pulse width resulting from a strike. The RTL or netlist combined with technology parameters will provide a statistical sensitivity in logic blocks and potential vulnerabilities. Final applications combined with an emulation platform will provide a final soft error rate. Phase two, Robustness Implementation, involves developing RTL code to embed fault tolerant IP. For SoC, this step may take advantage of previously developed Robust Cores in a library. Phase three, SER Qualification, performs radiation testing on the final die to qualify the IC before going into full production.
SERTEST is used in both Risk Assessment and SER Measurement.
SERTEST PRODUCT LINE ORGANIZATION
Pricing And Availability
SERTEST product line ranges from $30,000 for a regular alpha test to $80,000 for a SEUPROBE IP hard core. SMARTESTBED equipment for an alpha or cosmic ray test procedure will be also available starting at $60,000. The radiation test product and services package will be available before the end of June in the US and Europe for a price to be quoted from iRoC depending on the application.