May 31, 2002 - Genesys Testware, Inc., a leading supplier of embedded test solutions, announced today the availability of their latest product BSCANmaker™. BSCANmaker simplifies the top-level System on Chip (SoC) integration process by enabling designers to simultaneously insert IEEE 1149.1 compatible boundary scan and pad rings at the top-level of hierarchy. Traditionally, boundary scan and pad ring insertion have been separate steps in the design process, making it highly tedious and error-prone.
Many SoCs contain analog interface blocks such as Analog-Digital Convertors (ADCs), Digital-Analog Convertors (DACs), Serializer-Deserializers (SERDES) etc. It is difficult to test these analog nets using boundary scan tests at the board level with the current generation of chip level boundary scan insertion tools. BSCANmaker enables the testing of inter-chip analog interfaces using standard digital IEEE 1149.1 tests at the board level. BSCANmaker can also simplify the analog interface testing of an SoC if it contains pairs of analog interfaces that can be looped back (e.g., ADC-DAC, SERDES, etc.).
Some SoCs use Built-In Self-Test (BIST) extensively for chip testing. Developers of advanced SoCs typically use BIST macros from different vendors (For example, Company X for memory BIST, company Y for logic BIST and company Z for PLL BIST). However, this creates a problem in interfacing the BIST macros to the Test Access Port (TAP). The current boundary scan insertion tools in the market do not properly support BIST macros. BSCANmaker however, provides different instruction sets to support different types of BIST circuits.
"An advanced boundary scan tool that performs pad synthesis, enables the testing of analog interfaces and performs BIST integration is needed for complex SoCs. BSCANmaker was created to meet this need," said Bejoy G. Oomman, President of Genesys Testware. "We can now provide a more complete solution to our customers by offering BSCANmaker (advanced boundary scan) along with our popular MBISTmaker (embedded memory test and repair) product," continued Mr. Oomman.
MBISTmaker is also very easy to use for designers. The user writes short scripts in Tcl to describe the ports of the design and their attributes. MBISTmaker then creates a top level version of the SoC containing pads, boundary scan registers and the test controller complete with RTL and gate level simulation scripts. It also creates synthesis scripts for both Synopsys Design Compiler and Cadence Envisio Ambit tools to map the logic to any standard cell library. In addition, it creates a WGL file for chip level testing of the boundary scan logic and a BSDL for board level testing.
MBISTmaker is available immediately. Pricing for MBISTmaker starts at $50,000 for a site license and from $15,000 for a single project license.
About Genesys Testware
Genesys Testware, Inc. provides a comprehensive suite of embedded test solutions that covers memory test, logic test and boundary scan. Its products are all silicon-proven in various customer designs. For more information, please visit the company's web site at http://www.genesystest.com