TSMC and Cadence Deliver 3D-IC Reference Flow for True 3D Stacking
SAN JOSE, Calif. -- Sep 20, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has collaborated with Cadence to develop a 3D-IC reference flow which features innovative true 3D stacking. The flow, validated on a memory-on-logic design with a 3D stack based on a Wide I/O interface, enables multiple die integration. It incorporates TSMC 3D stacking technology and Cadence® solutions for 3D-IC, including integrated planning tools, a flexible implementation platform, and signoff and electrical/thermal analysis.
3D-IC technology enables companies to seek power/performance advances by opening up a new opportunity in addition to moving to advanced geometries. Offering several key benefits for engineers developing today’s complex designs, 3D-ICs deliver higher performance, reduced power consumption, and smaller form factor. Today’s announcement follows work the two 3D- IC leaders announced a year ago with the delivery of TSMC’s CoWoS™ Reference Flow.
“We have worked closely with Cadence to enable true 3D chip development,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With this new reference flow, our mutual customers can move forward confidently with 3D-IC development, knowing that their Cadence tool flow has been validated in silicon with 3D-IC test vehicles.”
“3D-IC represents a dramatic new approach to product integration. It provides a new dimension to Moore’s Law and requires a deep collaboration for a seamless enablement offering,” said Dr. Chi-Ping Hsu, chief strategy officer and senior vice president of the digital and signoff group at Cadence. “This latest reference flow demonstrates real progress in our work with TSMC to make 3D chips not just viable, but an attractive option for addressing chip complexity.”
Tools in the Cadence 3D-IC flow span digital, custom/analog and signoff technologies. They include Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Virtuoso® Layout Editor, Physical Verification System, QRC Extraction, Encounter Power System, Encounter Test, Allegro® SiP, and Sigrity™ XcitePI/PowerDC.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
|
Related News
- TSMC Validates Cadence 3D-IC Technology for Its CoWoS Reference Flow
- UMC and Cadence Collaborate on 3D-IC Hybrid Bonding Reference Flow
- Siemens collaborates with Intel Foundry to contribute 3D-IC technology leadership for Intel's EMIB reference flow
- GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform
- Cadence Expands Collaboration with Samsung Foundry, Providing Differentiated Reference Flows Based on the Integrity 3D-IC Platform
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |