Altera's SONET/SDH Solution Speeds Time-to-Market for Optical Network Applications
San Jose, Calif., June 3, 2002 — Altera Corporation (Nasdaq: ALTR) today announced the release of its SONET/SDH Compiler, the programmable logic industry's first fully programmable SONET/SDH framing and overhead processing solution for optical networks supporting optical levels up to OC-48. The SONET/SDH Compiler can be used for system-on-a-programmable-chip (SOPC) designs utilizing Altera's Stratix™ and APEX™ II family of programmable logic devices (PLDs), delivering a rapid, cost-effective solution for line rates up to 2.5 Gbps.
"Integrating SONET and other intellectual property (IP) functions in Altera's PLDs allowed us to quickly develop a flexible, reconfigurable SONET framing and overhead processing solution supporting optical levels up to OC-48," said Mike Downs, director of engineering at Adaptive Micro-Ware, an Altera Consultants Alliance Program (ACAPSM) member and user of the SONET/SDH Compiler. "The cost-effectiveness and reduced design times delivered by Altera's SONET solution allows telecom engineers to use programmable logic at even faster SONET rates."
The SONET/SDH Compiler is delivered with Altera's user-friendly MegaWizard® graphical user interface, allowing designers to optimize the IP to meet their exact system needs, reducing unit costs and simplifying the software integration. Altera's OpenCore® free test drive program allows designers to perform functional simulation, place-and-route, and static timing analysis before purchasing the IP.
"Service providers continue to look for cost-effective systems that support the wide range of transport protocols used in today's wide area networks," said Justin Cowling, Altera's director of IP marketing. "Implementing SONET functions with users' proprietary logic leads to highly integrated, flexible system solutions that can be brought to market with the shortest possible design cycle."
About the SONET/SDH Compiler
Altera's SONET/SDH Compiler supports line rates from STS-1/STM-0/AU-3 to STS-48c/STM-16/AU-4-16c, and both STS-1 and STS-3c/STM-1/AU-4 channelization. Altera's ATM Cell Processor Compiler is also available, providing ATM transmission convergence at up to 2.5 Gbps.
The ATM and SONET/SDH cores can be targeted for Altera's recently announced Stratix device family, the industry's largest and fastest PLD. The Stratix device family is based on a 1.5-V, 0.13-µm, all-layer-copper process technology and offers up to 114,140 logic elements (LEs), 10 Mbits of embedded memory, and high-performance I/O capabilities.
For more information on Altera ACAP partner Adaptive Micro-Ware, visit http://www.altera.com/acap/acp-adaptive.html
About Altera
Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.