Vivado Design Suite 2013.3 extends design flows and revolutionizes IP ease of use
SAN JOSE, Calif., Oct. 23, 2013 -- Xilinx, Inc. (NASDAQ: XLNX) today released the Vivado Design Suite 2013.3, featuring support for the new UltraFast™ design methodology, enhanced configuration, integration and verification of Plug-and-Play IP, and Partial Reconfiguration. The Vivado® Design Suite is co-optimized with Xilinx's All Programmable devices and is the programmable industry's only SoC-strength design suite able to address the productivity bottlenecks in system-level integration and implementation.
Automated Support for the New UltraFast Design Methodology
To enable accelerated and predictable design cycles, Vivado Design Suite 2013.3 provides built-in automation of critical aspects of the UltraFast design methodology, providing design rule checks (DRC) guiding engineers throughout the design cycle and HDL and constraints templates enabling optimal quality of results.
Enhanced Configuration, Integration, and Verification of Plug-and-Play IP
Xilinx's Plug-and-Play IP initiative, introduced in 2012, leverages industry standards such as IP-XACT, IEEE P1735 encryption and the AMBA® AXI4 interconnect protocol to accelerate integration of IP. Earlier this year, the Vivado Design Suite shattered the RTL design productivity plateau by providing the industry's first plug-and-play IP integration design environment with its IP Integrator capability.
The Vivado Design Suite 2013.3 release adds a major ease-of-use improvement with enhanced IP integration and offers over 230 LogiCORE™ and SmartCORE™ IP cores. This release upgrade allows for system-wide co-optimization of a design and Xilinx IP. For instance, designers can now share clocking resources throughout their design with connectivity IP such as Ethernet MAC or PCIe®. Upgrades to the IP also provide easy top-level access to transceiver debug ports within the IP. With new capabilities to the Vivado logic analyzer, designers have full read-and-write access to their AXI system, at runtime. They can also perform hardware debug using advanced trigger feature to detect and capture complex events.
This release also further eases the IP integration with revision control systems and automates the verification flows with the Cadence Incisive Enterprise simulator and the Synopsys VCS simulator.
The Vivado Design Suite 2013.3 introduces support for Partial Reconfiguration, which has been successfully used by many customers with the ISE Design Suite. This technology enables greater usage of device resources by dynamically swapping functions on demand. Partial Reconfiguration can also result in lower power consumption and can enable field updates with no system downtime.
"Utilizing Xilinx's Partial Reconfiguration feature in Vivado for 7 series devices has empowered Trendium to achieve a successful system on chip architecture while simultaneously meeting our PCI Express® requirements," said Stephen Frey, Firmware Engineering Manager at Trendium, Inc. "Partial Reconfiguration has allowed us to more efficiently utilize Xilinx silicon by interchanging protocol analysis modules for our Network Access Agent platform without disrupting the PCI Express link. This approach also provides a path to upgrade the existing hardware with new modules for future product enhancements."
Download the Vivado Design Suite 2013.3 today at www.xilinx.com/download. Sign up for or view online training for Vivado Design Suite, and take advantage of the UltraFast design methodology and the Vivado Design Suite-based Targeted Reference Designs to jumpstart your productivity.
Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com.