Grenoble, France -- October 25, 2013 -- Dolphin Integration, the innovator of Virtual Components for optimizing power-consumption and density of subsystems, today announces the latest generation of 6-Track standard cell libraries in mature processes, with enhanced features to enable further power and area savings with also timing improvements.
Designed around ultra dense sequential cells, celebrated as the patented spinner cell system, this new generation of 180/130 nm standard cell library now features:
- Buffer cells for balanced clocks to reduce clock skew by 20% and latency by 30% compared to the previous library generation, yielding a better density and less power consumption on clock network
- Improved design of the spinner cell system (pulse generator + spinner cell) for higher power and density gains after clock tree synthesis
- New combinatorial cell design to reduce silicon footprint
- Optimized characterization algorithm with more accurate set-up and hold time estimates, combined with the addition of high-drive cells, leading to an improvement of timings.
On a complete 60 kgates logic circuit, the new generation of uHD-BTF standard cell library has demonstrated 25% less power consumption and a density increased by 12% compared to the previous release.
“This updated uHD-BTF standard cell library expresses our vision for the future of mature processes. Everything from the cells to the user manual has been revamped to facilitate integration and to improve the PPA. There is no standard cell library like it for 180 nm and 130 nm processes”, concluded Elsa BERNARD-MOULIN, Dolphin Integration’s Library Marketing Manager.
For more information on the key benefits and performances of SESAME uHD-BTF standard cell library, have a quick look at:
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.