SAN JOSE, Calif., 25 Nov 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the company has received two Customers’ Choice Awards for papers delivered at TSMC’s recent Open Innovation Platform (OIP) Ecosystem Forum. The papers were entitled, “Resistance, Pin Access and FinFET Parasitics,” authored by Paul Cunningham, Rachid Salik, Hitendra Divecha and Rahul Deokar; and “16G Multi-Standard SerDes IP in TSMC’s 16nm FinFET Process,” authored by Eric Naviasky, Tom Wilson, Bob Salem and Jason Chen.
The awards were based on surveys completed by conference attendees.
“Our customers appreciate and benefit from the work Cadence is doing to bring 16nm FinFET design to market,” said Suk Lee, TSMC senior director of Design Infrastructure Marketing. “These technical papers move the ball forward by helping leading innovators embrace the most advanced manufacturing processes available.”
The papers can be viewed and downloaded from TSMC Online™.
Cadence previously announced that the company received three TSMC Partner of the Year awards at the OIP conference for work with TSMC on analog/mixed signal IP, 16nm FinFET design infrastructure, and 3D-IC design solutions.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.