Santa Clara, Calif. --(BUSINESS WIRE)--June 4, 2002--Tharas Systems, Inc., a provider of high-performance, hardware-assisted design verification solutions, announced today that Sun Microsystems, Inc. has purchased a Hammer8M simulation hardware accelerator.
"Sun evaluated the Tharas simulation acceleration hardware solution and identified verification domains where it could benefit from such technology. The Tharas/Hammer 8M support for industry standard software simulators and debug capabilities, which an engineer is familiar with, is important", says Sunil Joshi, vice president, Design Automation and Compute Resources, Processor Products Group, Sun Microsystems.
"The computing industry represents a major Verilog acceleration market for Tharas Systems. We are pleased that Sun Microsystems chose Hammer. Hammer, with its breakthrough processor-based technology, offers a superior solution in terms of compile times, run times, debug features, ease of use and scalability,'' notes Prabhu Goel, Chairman & CEO of Tharas Systems.
Tharas Systems' Hammer provides Verilog simulations with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Compile times are as fast as 5 minutes per Million RTL Gate-equivalent. Run times range from 10 to 1000 times faster than software simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug.
Hammer works with existing RTL and gate-level verification environment. As a result, designers may continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (Nasdaq:SNPS - news), and Cadence Design Systems, Inc. (NYSE:CDN - news)
Hammer hardware supports design sizes of up to 128 Million Gates-equivalent RTL and gate-level, and multiple memory models of up to 16 Gigabyte.
About Tharas Systems
Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer? offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/.
Hammer is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.