Designer of high performance interface IP expands offering targeted towards memory applications
SAN FRANCISCO, CA – June 10, 2002 –TriCN, a leading developer of intellectual property (IP) for high-speed I/O interface technology, today announced the availability of a QDR SRAM interface solution. This high-speed interface augments TriCN's portfolio of interfaces targeted towards memory applications, which also includes DDR SRAM and DDR SDRAM. TriCN's QDR SRAM interface solution is available for both Class I and II High Speed Transceiver Logic (HSTL) devices, and is based on a standard advanced by the Joint Electronic Device Engineering Council (JEDEC). TriCN's QDR SRAM product is available in Taiwan Semiconductor Manufacturing Company's (TSMC) 0.18 ?m process and several variations of its 0.13 ?m processes, including the 1.0V core supply (low voltage) process.
"Our QDR SRAM solution supplies one more piece of the puzzle in our effort to offer a complete portfolio of I/O products, not only for producers of memory products, but for a broad range of applications," explains Ron Nikel, CEO and Chief Technology Officer with TriCN. "Our goal is to become the single source for companies seeking interface solutions, whether in the memory, networking or communications space."
TriCN's QDR SRAM interface solution leverages the company's unique interface-specific approach to I/O, which gives its customers a significant implementation edge. Designers looking for a specific I/O interface find that most suppliers deliver solutions for a generic I/O interface technology, such as HSTL that do not meet their performance requirements. This leaves the customer designers with the burden of re-engineering the generic solution to fit their specific application. TriCN, by contrast, delivers HSTL already optimized for specific interface types – in this case, QDR SRAM, saving valuable development time and money for their customers.
Interface-specific I/O is TriCN's unique approach to distinguishing its suite of high performance interfaces from what's available from generic I/O IP providers. "The work we've done to produce interface-specific solutions frees up our customers from having to take on additional engineering tasks which not only impacts resources, but time-to-market," says TriCN's Nikel.
The QDR SRAM interface solution consists of HSTL I/O pads including dedicated I/O drivers for Data, Clock and Address. Maximum operational frequency is 500 mb/s per I/O. An internal VREF generator is provided for wafer and module test applications.
Signal Integrity and Timing
Application of TriCN's rigorous system level signal integrity and timing (SIT) analysis ensures optimal and reliable performance of the interface. Each interface is qualified for timing completeness and signal integrity quality for a full range of PCB impedance, PCB route lengths, terminator tolerance, and topology for given operational frequencies and memory sizes, assuring optimal and reliable performance. As an option, delivery may include system layout application notes, as well as comprehensive information for board layout of the pads and PCB and interconnect subsystem. An HSPICE analysis environment can also be made available, allowing customers to perform further analyses as modifications are made to the system.
TriCN's QDR SRAM interface solution is available now.
Founded in 1997, San Francisco, California-based TriCN is the creator of a new class of intellectual property (IP) known as Interface-Specific I/O. This IP is designed for IC developers addressing strategic, bandwidth-intensive communications, networking, storage and memory applications whose data throughput performance is currently stymied by I/O bottlenecks. TriCN's patent-pending technology overcomes these I/O bottlenecks by delivering validated, industry-leading I/O performance and bandwidth density while dramatically streamlining design complexity and time-to-market. With nearly 50 clients, including Nokia, Philips, MIPS Technologies, SGI, IBM and Apple Computer, TriCN maintains core competencies in high-performance I/O, signal integrity, circuit design and layout. For more information, please visit TriCN's web site at www.tricn.com.