Dolphin Integration launches new AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM

Grenoble, France – December 16, 2013 -- With the goal of improving drastically the PPA mix (Power x Performance x Area) of Non Volatile Memories (NVM) like eFlash or EEPROM, Dolphin Integration announces today R-Stratus-LP, new generation of cache controller.

R-Stratus-LP provides advanced NVM based devices architecture with outstanding gains:

• Power consumption of embedded or external NVM may be divided by 3X
• Apparent frequency is accelerated by 3X

R-Stratus-LP is indeed the first L1 Cache Controller with an architecture optimized for Low-Power

• Architecture designed to minimize the number of accesses to TAG and cache RAM and NVM memory
• cache line size and associativity both runtime programmable on the fly

This cache controller has also been designed for facilitating its use by SoC integrators

• Support of AHB-Lite interfaces to ensure easy integration within any MCU subsystem without need for any bridge
• Separation of TAG and cache RAM memories from R-Stratus logic in order to ease portability across a wide range of process technologies.

For more information about this offering, have a look at the presentation sheet

Our Application Engineer may help you appreciate fast the expectable improvements thanks to R-Stratus-LP cache controller based on your current NVM specification. Just click here or contact marketing.symphonie@dolphin.fr for more information.

About Dolphin Integration

Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. Such diverse experience in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, makes them a genuine one-stop shop covering all customers’ needs for specific requests.

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