Quickturn and TransEDA Collaborate to Increase IC Design Verification Speed
Design Automation Conference, New Orleans, LA. (U.S.A.) -- June 10, 2002 -- TransEDA PLC, the leader in ready-to-use verification solutions for electronic designs, announced that TransEDA's VN-Cover Emulator is now available for the Palladium design verification system from Quickturn, a Cadence Company.
VN-Cover Emulator is the industry's first coverage solution for hardware-assisted verification systems, providing a seamless coverage environment between simulation and emulation. The Quickturn Palladium system supports both simulation acceleration and in-circuit emulation and is ideal for verifying chips and systems prior to tape-out.
With verification dominating IC development schedules and resources, many companies -- especially those in networking, telecommunications, graphics, microprocessors and digital signal processing -- are adopting hardware-assisted verification as part of their strategy to shorten verification schedules. Measuring which parts of the design have been adequately verified and which may require additional attention is crucial to a complete verification process. VN-Cover Emulator on Palladium provides for the first time a complete, objective measure of how well a design has been verified and which parts of a design have been under-tested.
"Our customers always need to increase design productivity to stay competitive," said George Zafiropoulos, vice president of marketing, Quickturn. "The Palladium system provides superior compile and run-time performance for simulation acceleration and emulation. With the addition of VN-Cover Emulator, Palladium can further speed verification and provide greater assurance of first-pass silicon success."
"Our continuing cooperative efforts with TransEDA are representative of Quickturn's commitment to developing and delivering complete verification environments to speed our customers' time-to-market," said Zafiropoulos.
"We're pleased to work with market leader, Quickturn, to provide an enhanced solution for IC verification," said Tom Borgstrom, vice president of marketing at TransEDA. "This is just our first step in leveraging the power and performance of Palladium."
VN-Cover Emulator Accelerates Verification with Complete Coverage
High-performance Support for Many Simulation Options: VN-Cover provides support for a complete range of simulation acceleration options, from accelerated co-simulation with C/C++, to behavioral test benches and the market-leading Cadence NC-Sim mixed-language simulator. For the highest performance, Palladium can be used for synthesizable test bench acceleration, vector regression, and in-circuit emulation. No other single system can provide this choice of methods.
Smoothest Design Flow: Optimized instrumentation and Palladium's rapid compile time and easy-to-use environment ensure a smooth design flow with synthesizable instrumentation tuned for Palladium.
Higher Confidence in Design Quality: With an objective measure of verification progress, users can more efficiently load and use Palladium and see how completely a design has been verified before sign-off.
Thorough Verification: VN-Cover on the Palladium system quickly identifies verification holes including best- and worst-instance analysis. It also enables users to quickly see which areas need more testing, and to thoroughly assess the verification plan. Seamless integration between results from NC-Sim and Palladium gives a complete picture of the verification process, ensuring the use of the correct verification engine at each step.
About TransEDA's Verification Navigator
VN-Cover Emulator is available as part of the TransEDA Verification Navigator Integrated Design Verification Environment. In addition to coverage analysis for simulation and hardware-assisted systems, Verification Navigator includes VN-Property DX Dynamic Property Checking, VN-Control Application Specific Test Automation, VN-Check Configurable HDL Checking, and VN-Optimize Test Suite Analysis.
TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs.
The company's verification IP library includes models and properties for advanced microprocessors and bus interfaces. TransEDA's design verification software performs application-specific test automation, configurable HDL checking, code and finite state machine (FSM) coverage analysis, dynamic property checking, and test suite analysis.
TransEDA's tier-one list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, email email@example.com.
Note: TransEDA and Verification Navigator are registered trademarks and VN-Cover, VN-Check, VN-Control, VN-Property DX, and VN-Optimize are trademarks of TransEDA. Cadence is a registered trademark and Quickturn, Palladium, CoBALT, and CoBALT Plus are trademarks of Cadence Design Systems, Inc. All other trademarks are properties of their respective holders.