Software release features new 100G reference designs
SANTA CLARA, Calif., February 13, 2014 – Tabula, Inc., announced today the availability of version 2.8.2 of its Stylus® compiler, supporting its ABAX®² P-Series of devices. Stylus 2.8.2 includes a new 3 × 40G-to-100G low-latency Ethernet bridge reference design, as well as a high-performance search engine soft IP core developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience.
The new capabilities and design kits introduced in the Stylus 2.8.2 release include:
More about Stylus compiler
Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture; unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.
Availability:
Stylus version 2.8.2 is available today.
About Tabula:
Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com