ANDOVER, Mass. Avery Design Systems has folded a Verilog and C-language testbench-automation tool that works with third-party simulators into its TestWizard offering. The capability had been bundled with a proprietary Verilog simulator as part of the company's VCK product.
TestWizard is part of Avery's new SimLib product series, aimed at industry-standard Verilog simulators. Avery's SimCluster distributed-verification solution, launched earlier this year, made VCK's parallel-processing capability available for third-party simulators.
"We realized that people liked what we were doing with testbench automation and distributed simulation, but we did not want to consider bringing in another Verilog simulator," said Chris Browy, vice president of sales and marketing. "So we decided to take some of the core functionality and break it out of VCK."
TestWizard's Verilog capabilities are based on Avery' s proprietary Verilog Language Extensions. The VLE extensions use data types and functions that let designers build testbenches at a high level of abstraction.
"Basically, we've added a series of Verilog task and function calls that a user will build into his testbench," said Browy. "We've added some higher-level data types that make transaction-based verification more possible."
VLE provides such extensions as user-defined record and list of data types, multivariable constrained random-case generation, temporal protocol assertions, semaphore functions, and transaction and signal history buffering. It also provides functional coverage analysis.
Wider protocol checking
The transaction buffering, a feature not in the initial VCK release, lets designers load data into a transaction buffer and retrieve it whenever they want to, Browy said. TestWizard also has expanded protocol checking, more-complex temporal logic and more-readable reports, he added.
TestWizard's C/C++ capabiliti es come from Avery's Verification Collaborative Infrastructure, a high-level application programming interface that promises to be easier to use than the Verilog programming language interface.
The API claims to speed integration of intellectual-property blocks, since IP models developed in C/C++ can be connected to Verilog simulation with VCI.
Avery plans to propose VLE and its API to the Accellera standards organization, which is trying to come up with a property language, Browy said. He said that VLE offers such a capability with its temporal assertions.
TestWizard works with Cadence Design Systems' NC-Sim and Verilog-XL releases 3.1 and higher, and Synopsys' VCS release 5.2 and higher. It's available now on Solaris and Linux platforms starting at $7,500 for node-locked versions.