Rick Merritt, EETimes
3/19/2014 06:05 PM EDT
SAN JOSE, Calif. — GlobalFoundries will describe, in May, a way to make 3D chip stacks without a large keep-out zone around its through-silicon vias. The work is being hailed as an advance in silicon integration at a time when Moore's Law is slowing getting more costly.
In a paper at the IEEE International Interconnect Technology Conference in San Jose, GlobalFoundries will describe a middle-of-line (MoL) chip stack in a 20 nm planar process, which achieves a "near-zero" keep-out zone around its TSVs. Prior work used keep-out zones measuring seven microns or larger, wasting silicon space and driving up chip costs.
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