HDL Design House Announces JESD204B PCS Tx IP Core HIP 600

Belgrade, Serbia – April 1st, 2014 – HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced the availability of its JESD204B PCS Tx IP core (HIP600). The silicon proven JESD204B PCS Tx IP core, available now in various process nodes and technologies, is developed for a wide range of applications, such as wireless transceivers, signal processing cards, industrial, test and medical equipment.

The JESD204B interface defines high-speed serial interconnections and provides a method to connect one or multiple data converters to a digital signal processing device. This interface runs at up to 12.5 Gbps per lane, and uses a framed serial data link with embedded clock and frame/lane alignment characters.

The HIP 600 enables high performance data transfers in compliance with the JESD204B.01 standard release. This is a flexible and highly configurable solution that enables reliable interface for the Tx side, and supports a wide range of data converters over a single or multiple serial lanes. The HIP 600 performs data mapping, scrambling, alignment character insertion and 8b/10b encoding function. This IP core uses an AMBA APB4 interface for configuration setup and status reading purposes. It includes programmable debugging features, but also contains a set of test features and offers a variety of test patterns, necessary to validate the data integrity on the serial interface.

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