Cadence Offers Immediate Availability of DDR4 PHY IP on TSMC 16nm FinFET Process
SAN JOSE, Calif., May 19, 2014—Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced immediate availability of DDR4 PHY IP (intellectual property) built on TSMC’s 16nm FinFET process. The combination of 16nm technology and Cadence’s innovative architecture helps customers realize the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, as compared to today’s maximum of 2133Mbps for both DDR3 and DDR4 technologies. This technology enables server, network switching, storage fabric and other systems on chip (SoCs) requiring high-memory bandwidth to design-in Cadence® DDR4 PHY IP now and to exploit higher speed DRAMs when they become available.
The Cadence DDR4 PHY IP supports an unbuffered dual in-line memory module (UDIMM)/ registered dual in-line memory module (RDIMM) with reliability, availability, and serviceability (RAS) features such as cyclic redundancy check (CRC) and data bus inversion (DBI). The new DDR4 PHY IP implements architectural innovations such as 4X clocking to minimize duty cycle distortion, multi-band power isolation for increased noise immunity, and I/O with slew rate control. The Cadence DDR4 PHY IP together with Cadence DDR4 controller are verified in silicon from TSMC’s 16nm FinFET process.
“The demand for 16nm FinFET-based designs continues to grow and is driving the market need for a complementary DDR4 IP offering,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Because we have worked very early and closely with Cadence on this technology, our customers can review the design’s silicon results to feel confident about turning to Cadence for comprehensive 16nm support from tools to IP.”
“Many of our customers are concerned that their next-generation designs might not reach their performance goals because of the bottleneck in memory systems,” stated Martin Lund, Cadence’s senior vice president and general manager of the IP Group. “By using Cadence DDR4 IP, we believe our customers can have more confidence that their products will work with future DRAMs designed for higher speeds.”
DDR4 PHY IP is silicon-tested and available now. For more information on DDR IP, please visit http://ip.cadence.com/knowledgecenter/customize-main/ddr4-16ff
About Cadence
Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
|
Cadence Hot IP
Related News
- Cadence Announces DDR4 and LPDDR4 IP Achieve 3200 Mbps on TSMC 16nm FinFET Plus Process
- Cadence USB 3.0 Host Solution on TSMC 16nm FinFET Plus Process Achieves Industry Certification
- Cadence Digital and Custom/Analog Tools Achieve TSMC V1.0 DRM Certification for 16nm FinFET Process
- Alphawave IP Announces Immediate Availability of Advanced PCIe Gen1-5 PHY on TSMC's 7nm process
- Cadence Delivers IP for Automotive Applications with TSMC's Advanced 16nm FinFET C Process
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |