Will Outline Approach That Saves Hours, While Delivering Best Performance
SAN JOSE, CA – May 19, 2014 -
WHO: Uniquify, a leading high-performance semiconductor intellectual property (IP) and system-on-chip (SoC) design, integration and manufacturing services supplier
WHAT: Will demonstrate how its dynamic self-calibrating logic (DSCL) technology revolutionizes DDR memory subsystem IP design in a 10-minute mini-webinar for design engineers who want to learn how the technology is unlike any other on the market. The webinar, accessed by registration only, will outline an approach that saves hours and days of work, while offering the best performance currently available.
WHEN: Available for viewing now.
WHERE: The Uniquify website, found at: www.uniquify.com. To register, go to: http://tiny.cc/m0lxfx.
Uniquify is a rapidly growing system-on-chip (SoC) design, integration and manufacturing services supplier, and innovative developer of high-performance semiconductor intellectual property (IP) offering the world’s fastest DDR memory IP. Its “ideas2silicon” services range from specification development and front-end design through physical design and delivery of packaged, tested chips. It offers 65-, 40- and 28-nanometer SoC design expertise, integration and manufacturing services to leading semiconductor and system companies worldwide. Uniquify’s adaptive DDR subsystem IP offers the highest DDR performance with the lowest power, smallest area and the best system reliability — a result of its patented self-calibrating technology. Uniquify’s headquarters and primary design center is in San Jose, Calif., with additional design and technical sales and support teams in China, India, Japan, Korea and Vietnam. For more information, visit: www.uniquify.com.