Grenoble, France – May 26, 2014 -- Dolphin Integration provide users of 55 nm HV process with a new ROM architecture called TITAN.
Thanks to this new architecture, Dolphin Integration users can:
- reduce their die cost thanks to key patent for high density with a single metal programming layer, earning its qualifier of sROMet
- extend their battery life thanks to a minimal leakage in memory periphery
- facilitate integration with a large number of MUX options and high flexibility for address range
The ROM TITAN partakes in the TSMC sponsored offering at 55 nm HV, with the celebrated Single Port RAM RHEA and the Two Port Register File ERIS.
For more information about the sROMet TITAN TSMC 55 nm HV click here
Or contact Dolphin Integration Library Marketing Manager at email@example.com
About Dolphin Integration
Dolphin Integration contribute to "enabling mixed signal Systems-on-Chip". Their focus is to supply worldwide customers with fault-free, high-yield and reliable kits of CMOS Virtual Components of Silicon IP, based on innovative libraries of standard cells, flexible registers and low-power memories. They provide high-resolution converters for audio and measurement, regulators for efficient power supply networks, application optimized micro-controllers.
They put emphasis on resilience to noise and drastic reductions of power-consumption at system level, thanks to their own EDA solutions missing on the market for Application Hardware Modeling as well as early Power and Noise assessment. In addition strong experiences in ASIC/SoC design and fabrication, plus privileged foundry portal even for small or medium volumes, make them a genuine one-stop shop covering all customers’ needs for specific requests.
For more information, visit www.dolphin-integration.com