MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Silicon Highway Narrows, Twists
Rick Merritt, EETimes
6/30/2014 08:00 AM EDT
SAN JOSE, Calif. — The semiconductor road map is becoming as narrow and twisting as a mountain road, according to executives at two capital equipment companies. Chip vendors face higher costs and complexities due to tighter margins, new processes, and materials at 20 nm and beyond, they say.
In logic, foundries and their fabless customers have yet to settle on a new set of design rules. In memory, NAND flash has started a shift to 3D design other chips are likely to follow in some form, and DRAM faces a major materials shift, probably in 2015.
At 20 nanometers, the overlay budget of about 6 nm will shrink to about 4.5 nm while specifications for critical dimensions will narrow from 3 nm to 2 nm, says Brian Trafas, chief marketing officer at KLA-Tencor. He also predicts a 30% increase in process control spending between the 28 nm and 20 nm nodes to handle the requirements for multiple lithographic patterns needed to define some mask layers.
Chipmakers are using multi-patterning in four to ten mask layers starting at 20 nm and the follow-on node. In addition, these nodes are adding on a number of new deposition and etch steps, Trafas tells us.
E-mail This Article | Printer-Friendly Page |
Related News
- Accent Launches "Highway to Silicon"
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- StarIC and GlobalFoundries announce strategic partnership, release high-Speed TIA and drivers to advance silicon photonics ecosystem
- Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley
- Marvell Announces Industry's First 2nm Platform for Accelerated Infrastructure Silicon
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024