Calypto Catapult High-level Synthesis Platform Chosen by Olympus for C-Based Design and Verification

SAN JOSE, Calif.-- August 04, 2014 -- Calypto® Design Systems, Inc., a leader in low-power RTL design and C-based design and verification, today announced that Olympus Corp., a leading provider of digital imaging technology solutions, has selected Calypto’s Catapult high-level synthesis (HLS) platform for their advanced ASIC designs. Olympus evaluated several HLS tools and determined that the Catapult platform was the ideal choice given its proven success in ASIC tapeouts, best C language support and integrated HLS verification methodology.

“After Evaluating Catapult for high-level synthesis, we found it was possible to shorten the design time for beginning designers because the Catapult GUI is very easy and intuitive to use,” said Tetsuya Kawasaki, Deputy General Manager SOC Technology Department of R&D Division, Olympus. “We also found that Catapult would give us both the quality and productivity we needed, and we were able to develop very complicated IPs to be included in our ASIC in a very short turnaround time.”

The SoC Technology Department of Olympus is the division which evaluates new technologies for SoC development associated with all of Olympus products and proposes them to SoC design teams. The next generation imaging blocks designed by this division represent core technology for Olympus, and are built into strategic products for the high-end imaging market.

“We are delighted that Olympus has adopted Calypto’s C-based design and verification solution,” said Sanjiv Kaul, President and CEO at Calypto. “Our Catapult platform is unique in its comprehensive approach to high-level synthesis with its integration of SLEC for verification, and support for both C++ and SystemC. The Catapult platform is also the only HLS platform that is production proven in over 1000 successful tapeouts.”

Besides Catapult’s superior dual language support, Olympus determined Calypto’s integrated HLS verification flow essential to speed verification time. The tight integration with Calypto’s SLEC product (sequential logic equivalency checking) allows users to formally prove that Catapult’s generated RTL is equivalent to the original C model thereby dramatically reducing the RTL verification effort. Catapult is also the first HLS tool to implement an assertion synthesis flow that allows Olympus to improve overall source level quality as well as design coverage.

Olympus’ investigations also lead them to conclude that Catapult has the greatest deployment worldwide and the largest number of ASIC tapeouts in production. Calypto’s ability to support the Olympus design efforts through its support technology center of excellence was an additional key decision criterion.

About Calypto’s Products

Catapult® high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro® platforms are used to design, verify and optimize complex ASIC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.

About Calypto

Calypto® Design Systems, whose customers include Fortune 500 companies worldwide, is a leading provider of tools for high-level synthesis, RTL power analysis and optimization, and sequential logic equivalency checking. High-level synthesis is an essential methodology for IP development where algorithms and implementations must evolve at a rapid pace, as often occurs in applications such as HEVC, image processing, and advanced communication products amongst many others. Calypto’s patented, deep sequential analysis technology finds low-power optimizations in RTL that other solutions miss, resulting in maximum power utilization. Calypto has offices in Europe, India, Japan, Korea, and North America with representation in China, Israel, and Taiwan.