IP Reaches Back To Established Nodes
As SoC developers shift backward to established nodes, steps can be taken to improve the IPs functionality.
Ann Steffora Mutschler, Semiconductor Engineering
August 7th, 2014
Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality.
IP certainly can be improved to work faster at older geometries, stressed Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact. IP area also can be traded off for performance. Techniques range from layout design optimizations, like using larger channel transistors, to architectural duplication of functional units.”
Related News
- PCIe 7.0 specification reaches "half way point"
- Unleash Next-Gen Speeds with Silicon-Proven USB 3.0 PHY IP Cores with Type-C Support in Multiple Process Nodes
- MIPS Aims to Give Back Control, for AI-Centric Compute
- Established "Advanced SoC Research for Automotive" with 12 companies, led by automotive manufacturers
- What Is Holding Back Neuromorphic Computing?
Breaking News
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- T2M-IP Unveils Revolutionary MIPI D-PHY & DSI Controller IP Cores with speed 2.5Gbps/lane, Redefining High-Speed Data Transfer and Display Interfaces
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |