IP Reaches Back To Established Nodes
As SoC developers shift backward to established nodes, steps can be taken to improve the IPs functionality.
Ann Steffora Mutschler, Semiconductor Engineering
August 7th, 2014
Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality.
IP certainly can be improved to work faster at older geometries, stressed Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact. IP area also can be traded off for performance. Techniques range from layout design optimizations, like using larger channel transistors, to architectural duplication of functional units.”
Related News
- Analog IPs Automate Integration, Tune to Fab Nodes
- Ceremorphic Introduces Custom Silicon Development for Advanced Nodes Using In-House Technology to Speed Customer HPC Chip Development
- Apple, AMD Back TSMC's Tripled Investment, Tech Upgrade in Arizona
- Consortium forms Rapidus to get Japan back into chip race at 2nm
- Qualcomm hits back at ARM over lawsuit
Breaking News
- Worldwide Silicon Wafer Shipments and Revenue Set New Records in 2022, SEMI Reports
- AI-designed Chips Reach Scale with First 100 Commercial Tape-outs Using Synopsys Technology
- Arm Q3 FY22 financial results
- ZeroPoint Technologies raises EUR 3.2 million in seed funding to reduce energy consumption of data centers by more than 25%
- QuickLogic Drives eFPGA Innovation with New Aurora™ Development Tool Suite
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |