September 1st, 2014 -- Digital Core Design, IP Core provider and System-on-Chip design house, celebrating in 2014 15th Anniversary, presents the DRPIC1655X IP Core, which is compatible with the industry standard PIC 16XXX, but… ensures 4 times faster architecture and 1 system clock instruction execution time. Thanks to its price and software simplicity, engineers can minimize the software development costs and enable easy portability across low to high-end platform.
The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory. It’s been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the PIC IP cores market. – Especially now, when we see more demand from IoT projects – explains Jacek Hanke, DCD’s CEO – efficient solutions like DRPIC1655X are the right answer, cause one can find them for less than $1 in 10K quantities. But of course FPGA netlist is also available.
The DRPIC1655X Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC1655X IP core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.
The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. - This situation requires the pipeline to be cleared and subsequently refilled – adds Hanke - This operation takes additional one clock cycle.
Last but not least, the DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD on-chip hardware debugger, which allow easy package validation, at each stage of SoC design flow.
Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.
More information: http://dcd.pl/ipcore/81/drpic1655x/
CPU Key Features:
- Software compatible with PIC16C55X industry standard
- Pipelined Harvard RISC architecture
o 4 times faster, compared to original implementation
- 35 instructions
- 14 bit wide instruction word
- Up to 32 kB of internal Data Memory
- Up to 64K Words of Program Memory
- Configurable hardware stack
- Power saving SLEEP mode
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Technology independent HDL Source Code
- 800 MHz virtual clock frequency in a 0.35u technological process