Tabula Ships Family of 100G Development Systems

Company achieves major milestone with first customer delivery of complete programmable system-level solutions, delivering leadership capabilities for high-performance packet processing

SANTA CLARA, Calif., September 10, 2014 – Tabula Inc., has announced its first shipments to customers of its 100G development systems based upon the industry's first 22 nm 3D programmable logic device (3PLD) manufactured by Intel. The family delivers leadership capabilities unmatched by existing ASSP and programmable solutions, overcoming the barriers to 100G deployment. Tabula achieves this breakthrough by enabling deep packet inspection at line rate and the routing and switching of multiple 100G streams on a single chip. Live demonstrations of the systems will take place at the company’s 2014 Intel Developers Forum booth, located within the Silicon Photonics section of the San Francisco Moscone Center on September 9-11th.

Highlights of these systems, along with examples of possible customization include:

• 12 × 10G-to-100G bridge: A low-latency12 × 10 GigE-to-100 GigE bridge providing transparent bidirectional bridging between the 10 GigE ports and the 100 GigE port. The bridge utilizes a deficit-weighted round-robin (DWRR) traffic scheduler for the aggregation of the 10 GigE ports. It includes a forwarding table for 100 GigE traffic and supports multicast, broadcast and jumbo packets. The bridge can be easily modified to support different port counts, port speeds, and interface standards, for example, to form configurations such as a 3 × 40 GigE-to-100 GigE bridge or a 10 × 10 GigE-to-100G Interlaken bridge.
• 4 × 100G L2-L4 switch: The only commercially available device supporting the switching of multiple 100G streams on a single chip. The low-latency 4-port 100G L2-L4 switch is designed for next-generation routers and data centers. It comes with a switch development board delivering 1.12 Tbps of bandwidth. Possible variations include other low-latency L2-L4 switch configurations such as a 64-port 10G and 16-port 40G versions.
• 100G RegEx accelerator: The world’s highest performing RegEx accelerator. Developed in collaboration with TitanIC Systems, this design is a 100 Gbps RegEx accelerator for next-generation firewalls and security appliances. It supports a sustainable throughput of 40 Gps and in excess of 1M rules, as well as advanced features such as cross packet inspection. The solution comes with TitanIC Cronus application software and rules compiler. Variations include 20 Gbps and a 5 Gbps RegEx accelerators, also developed in cooperation with TitanIC Systems.

Deliverables for each solution include:

• The ABAX2P1 3PLD mounted on its respective development board
• Stylus software featuring Tabula’s advanced sequential timing optimization
• Complete reference design in RTL form with testbenches
• Access to Tabula’s customer portal, including complete documentation and training, plus access to soft IP libraries

“Tabula’s 100G solutions demonstrate impressive capabilities,” said Richard Wawrzyniak, senior analyst at Semico Research Corp. “Time to market has a deep impact on a company’s market share, revenue and ultimately profitability. By offering complete system-level solutions, Tabula can significantly accelerate the design of advanced packet processing applications, improving its customers’ time to production and as a result, their bottom line.”

Availability:
Currently shipping to customers, the 12 × 10 GigE-to100 GigE bridge and its development board are available now, along with access to Stylus software. The 4 × 100G L2-L4 switch, the 100 Gbps RegEx accelerator, and their respective development boards will be available in Q4 2014. Customers interested in volume pricing can contact their local Tabula representative. http://www.tabula.com/contact/sales.php

About Tabula:
Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com