Complete 28Gbps SerDes Evaluation Platform with Board, Test Chip and Characterization Data
Milpitas, Calif., Sept. 16, 2014 – Open-Silicon today announced a 28Gbps Serializer/Deserializer (SerDes) evaluation platform for ASIC development that will enable the rapid deployment of chips and systems for 100G networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
“Silicon-proven IP, such as the advanced 28Gbps SerDes PHY developed by Semtech, is central to our success as a leading ASIC solutions supplier,” said Taher Madraswala, president of Open-Silicon. “In selecting IP and IP partners, we take into account not only the overall functionality within the IP and its compatibility with other IP blocks, but also its interoperability within the ASIC tool flow and how reliably it can be manufactured in a high-volume process technology. The Semtech 28Gbps IP satisfies our stringent third-party IP requirements, and provides our ASIC customers with a reliable path to meeting the needs of 100G networks.”
“Having silicon results at this important 25G+ threshold is essential for customers to move forward with their plans to develop ASICs for the 100G network build-out,” said Kevin Walsh, director of worldwide marketing, Semtech Snowbush IP Group. “With Open-Silicon, we have a partner that can develop these complicated chips. We have worked closely with Open-Silicon and our joint customers on all aspects of design – from concept through to fully, manufactured and tested parts, and with that experience, we can now provide a fast track to the delivery of chips and systems for 100G networks and beyond.”
About the Semtech 28G PHY IP
The Semtech SBMULTC2T28HPM28G PHY has an analog front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis. The PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power and latency have been optimized for use in SOCs, ASICs or ASSPs. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.
“Until now, network systems manufacturers have had limited access to fully tested and proven third-party 28G SerDes IP – especially at the 28-nm node,” said Richard Wawrzyniak, IP analyst with Semico. “Evaluation platforms are key to enabling advanced network ASICs and SoCs that can handle growing bandwidth requirements in data centers, driven primarily by increased demand for cloud storage and Internet of Things applications.”
Target Applications and Markets
As part of the Open-Silicon SerDes Technology Center of Excellence (TcoE) offering, the 28G SerDes is targeted for ASIC and SoC deployment in high-data-rate, chip-to-chip and chip-to-module applications. Open-Silicon applies its unique, high-speed serial design expertise to ensure the successful delivery of ASICs and SoCs for next-generation, high-speed systems used in the networking, telecom, computing and storage markets.
Packaging and Availability
The 28-nm test chip has been packaged in a 19mm x 19mm, 324-ball high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate. This package material was selected for its relatively wider trace characteristics, low loss tangent, and superior uniform via arrangements that minimize reflections in vertical transitions. Open-Silicon optimized the final package design through simulations to meet and exceed the guidance derived from the CEI specifications.
The 28Gbps SerDes evaluation platform will be available by the end of Q3 from Open-Silicon. Please visit www.open-silicon.com/serdes-technology-center-excellence for more information.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system and software – and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully shipped nearly a hundred million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com