Native SystemVerilog-based MIPI C-PHY Verification IP Broadens Synopsys' VIP Portfolio Enabling Verification of Full Family of MIPI Alliance PHY Options
MOUNTAIN VIEW, Calif., Sept. 17, 2014 -- Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of verification IP (VIP) for the MIPI® Alliance MIPI C-PHY™ specification that uses three-phase digital coding techniques to provide higher performance for camera, display and system-on-chip (SoC) interfaces without affecting bandwidth. Synopsys, a contributing member of the MIPI Alliance, provides VIP and design IP that accelerate the adoption of MIPI-based standards in mobile and mobile-influenced industries, including automotive and medical, that can leverage MIPI Alliance standards such as those for display, camera and sensor interfaces. The release of this new VIP helps enable engineers to verify interfaces such as MIPI CSI-2 v1.3, which includes the MIPI C-PHY. Synopsys VIP supports the MIPI Alliance protocol specifications including D-PHY, C-PHY and M-PHY and is based on a native SystemVerilog architecture for enhanced ease of use, performance and debug, enabling compliance checking of IP blocks and SoC interfaces.
"As a global alliance that addresses the interoperability and high performance of electronic interfaces used in mobile devices, we are continually responding to the needs of our member companies with enhancements and innovations. The MIPI Alliance's development of the MIPI C-PHY specification was driven by the need to create an interface for peripherals with limited bandwidth while maintaining compatibility with the MIPI D-PHY™ implementations," said Joel Huloux, chairman of the board of MIPI Alliance. "The release of the Synopsys MIPI C-PHY verification IP strengthens the overall ecosystem that is required to enable fast development of products as design teams race to implement new functionality."
"We have collaborated extensively with leading-edge SoC design teams to address the increasingly demanding process of protocol compliance verification. The release of a new, faster and more sophisticated revision of a protocol creates challenges for design teams as they strive to rapidly verify compliance against the new specification," said Debashis Chowdhury, vice president of R&D, Synopsys Verification Group. "We continue to deliver solutions that enable designers to accelerate their SoC verification closure and decrease time to market. The Synopsys VIP for MIPI C-PHY provides engineers with a solution that includes the built-in protocol knowledge, features and methodology they need to save time, increase design quality and meet project schedules."
About Synopsys Verification IP
Synopsys VIP, based on its next-generation architecture and implemented in native SystemVerilog, offers native performance, native debug with its Verdi® tool, enhanced ease of use, configurability, coverage and source code compliance test suites. These capabilities substantially increase user productivity for one of the most difficult and time-consuming aspects of SoC design and verification. The Synopsys VIP library includes a broad portfolio of interface, bus and memory protocols. More information is available at www.synopsys.com/vip.
The Synopsys VIP for M-PHY, D-PHY and C-PHY are available today. C-PHY is included with the Synopsys VIP for CSI-2 v1.3.
Synopsys, Inc. (NASDAQ:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.