CAMBRIDGE, England and SAN JOSE, Calif., Sept 29, 2014 -- ARM® and Cadence today announced an expanded collaboration for IoT and wearable devices targeting TSMC's ultra-low power technology platform. The collaboration enables the rapid development of IoT and wearable devices by optimizing the system integration of ARM IP and Cadence's integrated flow for mixed-signal design and verification, and their leading low-power design and verification flow.
The expanded partnership grants rights to deliver reference designs and physical design knowledge for integrating ARM Cortex® processors, ARM CoreLink™ system IP, and ARM Artisan® physical IP along with RF/analog/mixed-signal IP and embedded flash into the Virtuoso®-VDI Mixed-Signal Open Access integrated flow for the new TSMC process technology offerings of 55ULP, 40ULP and 28ULP.
"TSMC's new ULP technology platform is an important development in addressing the IoT's low-power requirements," stated Nimish Modi, senior vice president of Marketing and Business Development at Cadence. "Cadence's low-power expertise and leadership in mixed-signal design and verification form the most complete solution for implementing IoT applications. These flows, optimized for ARM's Cortex-M processors including the new Cortex-M7, enable designers to develop and deliver new and creative IoT applications that take maximum advantage of ULP technologies."
"The reduction in leakage of TSMC's new ULP technology platform combined with the proven power-efficiency of Cortex-M processors can enable a vast range of devices to operate in ultra energy-constrained environments," said Richard York, vice president of embedded segment marketing, ARM. "Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market."
This new collaboration builds on existing multi-year programs to optimize performance, power and area (PPA) via Cadence's digital, mixed-signal and verification flows and complementary IP alongside ARM Cortex-A processors and ARM POP™ IP targeting TSMC 40nm, 28nm, and 16nm FinFET process technologies. Similarly, the companies have been optimizing the solution based around the Cortex-M processors in mixed-signal SoCs targeting TSMC 65/55nm and larger geometry nodes. The joint Cortex-M7 Reference Methodology for TSMC 40LP is the latest example of this collaboration.
For more information on ARM and Cadence collaboration activities attend ARM TechCon 2014, October 1-3 at the Santa Clara Convention Center. Papers are scheduled to be presented in the technical tracks as well as demonstrations at their respective booths in the exhibit.
ARM is at the heart of the world's most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.
Our innovative technology is licensed by ARM Partners who have shipped more than 50 billion Systems on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies. Learn more and join the conversation at http://community.arm.com.
About Cadence Design Systems
Cadence Design Systems (NASDAQ: CDNS) plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.