- ispXPTM Technology Provides Non-Volatile, Infinitely Reconfigurable In-System Programming
- Flexible Multi-Function Blocks Implement Wide Logic/RAM/FIFO/CAM Efficiently Based on User Applications
- New Approach Initiates Third Wave of PLD Architectures
HILLSBORO, OR - JULY 15, 2002 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the inventor of in-system programmable (ISPTM) logic products, today introduced its revolutionary ispXPLDTM (in-system programmable eXpanded PLD) architecture, the first PLD architecture that allows users to efficiently trade-off fast logic and block memory resources. The unique architecture allows each Multi-Function Block (MFB) to be used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16 kilobits per MFB), yielding up to 1024 macrocells or 512 kilobits of memory on a single device, equivalent to 300K system gates. The SuperWIDETM architecture also supports functions of up to 136 inputs in a single level of logic, doubling the fan-in of any other PLD family and providing fast support for extremely wide buses and logic functions. Performance of up to 285MHz, with pin-to-pin logic delay (tPD) of 3.5ns and clock-to-output delay (tCO) of 2.5ns, is specified.
The ispXPLD family also utilizes Lattice's new ispXPTM (ISP eXpanded programmability) technology that combines the traditional product-term based PLD benefit of "instant-on", non-volatile programming together with real time, unlimited reconfigurability found in SRAM-based FPGAs.
"This breakthrough architecture provides a convergence of device architecture and programming technology that will allow ispXPLD devices to cross over traditional programmable logic segment boundaries," stated Steven A. Laub, President of Lattice Semiconductor. "We now have devices that combine the speed, predictability and non-volatility of CPLDs together with the system-level features, density and reconfigurability of FPGAs. System designers will no longer have to compromise one for the other. As such, Lattice ispXPLD devices signal the start of a third wave of PLDs, destined to succeed its Simple PLD and Complex PLD predecessors."
The initial series of ispXPLD devices, the ispXPLD 5000MX family, will be available in 1.8, 2.5 and 3.3 Volt power supply versions, designated the 5000MC, 5000MB and 5000MV series. The devices will be offered in 256, 512, 768 and 1024 macrocell-equivalent densities with 141 to 381 user I/O, corresponding to 75K to 300K system gates. The first device, the ispXPLD 5512MX, packaged in a 484 fine pitch BGA (fpBGA) package, will sample shortly. Programmable sysIOTM interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, LVDS, etc.) support. Advanced silicon technology, combined with proprietary circuit design techniques, provides standby power consumption as low as 36 milliwatts per device for power-sensitive applications. Each device also incorporates Lattice's sysCLOCKTM PLL capability for high-performance on-chip clock synthesis.
The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously relegated only to FPGAs or ASICs. Potential application areas include high-performance bus bridges, intelligent backplane interfaces, protocol processors and the like.
Multi-Function Block Implements Macrocells or Memory Efficiently
The homogeneous ispXPLD architecture consists of a number of uniform Multi-Function Blocks interconnected by a single-level, high speed programmable Global Routing Pool (GRP). The GRP also connects the MFBs to the I/O cells. Devices in the ispXPLD 5000MX family integrate from 8 to 32 MFBs into a single device. Each MFB within an ispXPLD device can be programmed independently to implement 32 macrocells of SuperWIDE logic, an 8 kilobit Dual Port RAM, a 16 kilobit Single Port RAM or FIFO, or a 128 by 48 bit Content Addressable Memory (CAM). Dedicated FIFO control logic is included on-chip so programmable resources are not consumed providing these memory control functions. While the basic logic block configuration supports up to 68 logic inputs in a single level of logic, cascading MFBs allow the devices to support functions of up to 136 inputs without incurring an additional level of logic delay, further raising the bar for a wide logic architecture.
sysIO and sysCLOCK Capability for Board-Level Performance
Each I/O pin on the devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8 Volts). Four independent I/O banks provide support for multiple interface voltages and standards on a single device. Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost. Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The family also supports GTL+, PCI, LVDS and LVPECL I/O configurations for use in high-speed bus interfaces.
The ispXPLD devices have two sysCLOCK PLLs that provide precise timing control for today's high-speed designs. Designers can generate complex clock waveforms with the clock multiply and divide capability of the phase-locked loops, as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.
IspXP Technology - Non-Volatile and Infinitely Reconfigurable
Lattice's new ispXP technology enables its ispXPLD family (as well as its ispXPGATM FPGA devices being concurrently introduced) to combine programmability benefits found in both non-volatile PLDs based on electrically erasable technology as well as reconfigurable FPGAs based on SRAM technology. As a result, the devices feature: (i) "instant on" operation at system start-up, allowing them to support critical system "heartbeat" functions without external initialization; (ii) non-volatile in-system programming, thereby giving higher integration through the elimination of an external boot PROM; (iii) enhanced design security since programming bit streams are invisible at system initialization; and, (iv) infinite reconfigurability via an 8-bit microprocessor port or JTAG boundary scan port for the ultimate in system adaptability.
The ispXPLD 5000MX family is supported by Lattice's new ispLEVERTM v2.0 design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispXPLD devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Mentor Graphics/Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions. The ispLEVER design tools, including VHDL and Verilog synthesis tools, are available for download from the Lattice website.
Price and Availability
The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fpBGA package will sample later this quarter with initial production scheduled for Q4. Pricing for the ispXPLD 5512MC in volumes of >1000 pieces starts at $17.75. Additional members of the ispXPLD 5000MX family are expected to be released over the coming year.
About Lattice Semiconductor
Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISPTM programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
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Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperWIDE, sysIO, sysCLOCK, ispXP, ispXPGA, ispXPLD, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
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