Cadence Digital Solution Enabled GUC to Improve System Performance by 2X and Deliver 180 Million Gate SoC Design
SAN JOSE, Calif., October 20, 2014—Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, and Global Unichip Corporation (GUC), the Flexible ASIC LeaderTM, today announced that GUC used the Cadence® Encounter® Digital Implementation System to tape out its first production high performance computation ASIC design on TSMC’s 16nm FinFET Plus (16FF+) process. The combination of the Cadence digital solution with the 16FF+ process provided GUC with a 2X system performance improvement, an 18 percent frequency increase, and a 28% power reduction over their previous design.
GUC utilized the Encounter Digital Implementation System to address the implementation challenges that arise at 16FF+, including increased double-patterning and FinFET design rule checking (DRC), timing and power variability, and throughput requirements. In addition, the Encounter system provided:
- A correct-by-construction, comprehensive double-patterning and FinFET-enabled flow that spans floorplanning, placement, and routing to electrical and physical signoff
- Seamless integration with Cadence Litho Physical Analyzer and Cadence CMP Predictor to enable design-for-manufacturing (DFM)
- Multi-threaded GigaOpt and NanoRoute technologies that employed massive parallelization to effectively handle the increase in DRC rules and design size
- The GigaOpt advanced on-chip variation (AOCV) and route-driven technologies that improved the performance and power of the SoC
“As a leader in ASIC designs, we need to deliver very complex designs to our customers in a timely manner, and the Cadence tools and team have helped us do this,” said Jim Lai, president of Global Unichip Corporation. “We chose to work with Cadence on the development of our design because of their extensive experience with TSMC at advanced nodes. Before we completed our first full production tapeout, we also taped out several 16nm test chips using the Cadence tool set and experienced excellent silicon results. Thanks to the collaboration between the Cadence and GUC teams, we met an aggressive three-month design-to-tapeout schedule for our 180M gate production design.”
“Encounter Digital Implementation System is designed to provide the most effective methodology for 100M+-instance high performance and power-efficient designs,” said Anirudh Devgan, senior vice president, Digital and Signoff Group, Cadence. “The Encounter system has been validated by TSMC on the 16FF+ process, which gives GUC and other customers the confidence that they can achieve the fastest path to design closure at advanced nodes.”
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
GLOBAL UNICHIP CORP. (GUC) is the Flexible ASIC LeaderTM that provides the semiconductor industry with leading IC implementation and SoC manufacturing services. Based in Hsinchu Taiwan, GUC has developed a global reputation with a presence in China, Europe, Japan, Korea and North America. GUC is publicly traded on the Taiwan Stock Exchange under the symbol 3443. For more information, visit www.guc-asic.com.