MIPS Technologies Licenses Sony Computer Entertainment Inc.
MOUNTAIN VIEW, Calif., July 17, 2002 -- MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), a leading provider of industry-standard processor architectures and cores for digital consumer and business applications, today announced that its MIPS64™ architecture has been licensed to Sony Computer Entertainment Inc. (SCEI).
SCEI has long been a major user of MIPS® technology, largely in the PlayStation® family of products. The PlayStation®2 computer entertainment system contains two MIPS-based™ processors, including the 128-bit EmotionEngine® multimedia processor. MIPS-based processors also power the original PlayStation game console.
"SCEI is a world leader in the computer entertainment market and has long recognized the value of the MIPS architecture. We are proud to be at the core of development of SCEI's outstanding products, helping to enable a rich and rewarding user experience," said Kevin Meyer, vice president of marketing at MIPS Technologies.
About 64-Bit Architecture
MIPS Technologies began developing its 64-bit processor architecture more than 10 years ago, based on the leading-edge RISC (reduced instruction set computer) research of MIPS co-founder John Hennessy, currently the president of Stanford University. Today, MIPS Technologies is the only company that openly licenses 64-bit architecture. It also licenses synthesizable microprocessor cores based on that architecture. More than a dozen leading companies, including NEC, Toshiba, Broadcom, PMC-Sierra, IDT and LSI Logic have successfully deployed the technology in a variety of consumer and networking applications. They include the microprocessor for the Nintendo® 64 and the 128-bit EmotionEngine® processor for Sony Computer Entertainment's PlayStation®2 computer entertainment system. The growth in 64-bit processing is fueled by demand for features such as streaming audio and high-definition video for small and large displays, cryptography enhancements for e-commerce, better power efficiency and battery life in handheld devices, and the convergence of computing, communications, multimedia and encryption in new types of information appliances. The MIPS® architecture has the rare capability of executing 32-bit and 64-bit code, in binary form, on 64-bit processors without the need to recompile. This capability allows system designers to select from a broad range of commercially available 32-bit and 64-bit MIPS code to accelerate the development of high-bandwidth, next-generation 64-bit products.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com .
# # #
MIPS is a registered trademark in the United States and other countries, and MIPS64™ and MIPS-based™ are trademarks of MIPS Technologies, Inc. PlayStation and EmotionEngine are trademarks of Sony Computer Entertainment Inc. All other trademarks referred to herein are the property of their respective owners.
- Xilinx Acquires Assets of Falcon Computing Solutions to Advance Software Programmability and Expand Developer Community
- Nordic Semiconductor expands into Wi-Fi by acquiring the entire Wi-Fi development team, core Wi-Fi expertise, and Wi-Fi IP tech assets of Imagination Technologies Group
- Broadcom Debuts Industry's First 5nm ASIC for Data Center and Cloud Infrastructure
- De-RISC first anniversary, a H2020 project which will create the first RISC-V, fully European platform for space
- Intel to Keep Its Number One Semiconductor Supplier Ranking in 2020
|E-mail This Article||Printer-Friendly Page|