Delivers Critical IP to Address Growing Bandwidth Needs of Next-Generation Networks
MILPITAS, CA -- November 19, 2014 -- Open-Silicon today announced a comprehensive Hybrid Memory Cube (HMC) 2.0 controller solution as licensable Intellectual Property (IP) that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging memory standard. Building upon its experience in working with customers to integrate earlier generations of this critical memory controller interface, Open-Silicon now offers high-quality HMC IP and the sophisticated integration environment required to speed design, reduce cost and ensure product manufacturability. The company is already engaged with a lead customer to integrate the new HMC 2.0 controller IP into devices for applications such as high-speed networking equipment.
HMC is a revolutionary innovation in DRAM memory architecture that sets a new standard for memory performance, power, reliability, and cost. Governed by the Hybrid Memory Cube Consortium (HMCC), the specification fundamentally changes the way memory is built into a system by leveraging 3D packaging to connect multiple DRAM arrays to logic using through silicon vias (TSVs). The HMC 2.0 standard, recently ratified by the HMCC, specifies data rates up to 30 Gb/s.
"Our extensive background with both the integration of HMC IP and advanced design techniques is enabling a new generation of ASICs designed to address the growing bandwidth requirements of 100G and 400G networks, as well as high-performance computing," said Hans Bouwmeester, Vice president of IP and Engineering Operations at Open-Silicon. "As a developer member of the HMCC, we are actively involved in defining the specification, and can deliver standards-compliant IP as soon as the standard is ratified."
"Stacked DRAM and logic solutions, such as HMC 2.0, break through the memory bottleneck and deliver the performance and low-power needed by next-generation computing systems," said Jim Handy, memory analyst with Objective Analysis. "Integration-ready interface solutions like Open-Silicon's HMC controller IP should drive down the cost of deployment, and accelerate this transition."
About the Open-Silicon HMC 2.0 Memory Controller IP
The Open-Silicon HMC 2.0 memory controller IP is a licensable, soft macro implementation that is designed to be compliant with both HMC v1.0 and the upcoming HMC v2.0, supporting all of the defined data rates of both standards. The device seamlessly interfaces to leading third-party SerDes IP without the need for an additional PCS layer. Moreover, Open-Silicon's recently announced SerDes Technology Center of Excellence (TCoE) will provide ASIC customers a convenient and reliable way to verify and test the integration of the HMC 2.0 memory controller IP with SerDes. Supporting data rates of up to 480 GBytes/s, the IP offers a low latency and a flexible user interface. The IP is delivered with a comprehensive set of deliverables including a test bench with a generic HMC model. For more information about the Open-Silicon HMC 2.0 controller, please visit http://www.open-silicon.com/open-silicon-ips/hmc/ or e-mail us at IP@open-silicon.com.
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers' products by innovating at every stage of design -- architecture, logic, physical, system and software -- and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully shipped nearly a hundred million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com.