November 27, 2014 -- Sercos International, provider of the Sercos® automation bus, announced today the availability of the Sercos III IP Core for Altera's low-cost, low-power Cyclone® V devices.
The IP core is available for Sercos III master and slave controllers (SERCON100M/S). It includes all hardware functions, such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs. Sercos III master and slave devices can be implemented as a single chip solution using either Cyclone V FPGAs or Cyclone V SoCs, which integrate an ARM® dual-core Cortex™-A9 processor.
"The on-going use of the flexible and continually developing FPGA technology brings significant cost and performance benefits to the Sercos community", said Peter Lutz, Managing Director of Sercos International e.V.
"Using Altera's Cyclone V FPGA and SoC devices to implement a single-chip embedded Sercos III Industrial Ethernet Protocol with integrated PLC and motion control functionality enables faster time-to-market and significant performance advantages at a low cost for our factory automation customers", said David Moore, Director for the Industrial Business Unit, Altera Corporation.
Detailed documentation on the IP core, reference designs and example Ethernet interface diagrams are available from Sercos International. Technical support and customer-specific design services are provided by Cannon-Automata, Ried/Germany and Caronno, Pertusella/Italy (www.automataweb.com).
"Cyclone V FPGAs and SoCs facilitate a broad range of new application areas. The Cyclone V SoC, with its integrated ARM processor, delivers significant performance improvements for computing-intensive applications. For example, complete Sercos master devices can be implemented in the form of a single-chip solution", says Christoph Melzer, Managing Director of Cannon-Automata.
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