Altera's RapidIO Solution Speeds Time-to-Market for System-on-a-Programmable-Chip Applications
Smart Networks Developer Forum, New Orleans, July 22, 2002 -- Altera Corporation (NASDAQ: ALTR) today announced the release of its RapidIO Physical Layer MegaCore® function, the programmable logic industry's highest performing RapidIO™ interconnect solution. The RapidIO Physical Layer MegaCore function can be used for system-on-a-programmable-chip (SOPC) designs utilizing Altera's Stratix™ and APEX™ II FPGA families, delivering a rapid, cost-effective solution for systems requiring data and control processing at full-duplex rates of up to 8 gigabits per second (Gbps).
Altera's RapidIO Physical Layer MegaCore intellectual property (IP) function is configurable for 8-bit implementations at up to 840 megabits per second (Mbps) per low-voltage differential signaling (LVDS) channel, or 16-bit implementations at up to 500 Mbps per LVDS channel, and features Altera's Atlantic™ standard local interface. The RapidIO core will be featured at the Motorola Smart Networks Developer Forum, July 21-24, running on Altera's Stratix and APEX II FPGAs.
"Motorola continues to support the RapidIO interconnect standard, evidenced by today's disclosure of our next-generation MPC8560 communications processor as well as our MPC8540 communications processor released last year," said Raj Handa, director of PowerQUICC business development and technical marketing for Motorola's Networking and Communications Systems Division. "Altera's support of this leading technology demonstrates its commitment to the networking infrastructure, telecommunications and embedded markets."
Altera has participated in defining the RapidIO standard through its membership in the RapidIO Trade Association. The RapidIO standard is a high-performance, packet-switched interconnect technology designed to pass data and control information between microprocessors, digital signal processors, communications and network processors, system memories, and peripheral devices. The RapidIO specification defines physical-layer technology suitable for chip-to-chip and board-to-board interconnect across standard printed circuit board (PCB) technology utilizing 8-bit and 16-bit LVDS. RapidIO technology offers the bandwidth, software independence, fault tolerance, and low latency required by the telecommunication and data communication markets.
"Today's announcement signals Altera's continuing commitment to the emerging RapidIO standard and offers designers a solution for evaluating and integrating RapidIO connectivity into their SOPC designs," said Glenn Henshaw, director of Altera's Ottawa Technology Center.
Henshaw will participate in a panel discussion on the adoption of RapidIO technologies at the Motorola Smart Networks Developer Forum on the morning of Tuesday, July 23. In addition to a demonstration of the core running on Stratix, the Forum will also feature a functioning display of Altera's APEX II devices bridging the RapidIO and peripheral component interconnect (PCI) standards to a Motorola PowerPC mezzanine card running software from QNX Software Systems.
RapidIO MegaCore Pricing and Availability
A royalty free, node-locked perpetual license for Altera's RapidIO Physical Layer MegaCore function is available now for $17,995, order code IP-RIOPHY. The core is delivered with Altera's user-friendly MegaWizard® graphical user interface, allowing designers to optimize the core to meet their exact system needs. Combined with Altera's OpenCore® free test drive program, designers can optimize the IP core and perform functional simulation, place-and-route, and static timing analysis before purchase. To download the RapidIO Physical Layer MegaCore function, visit Altera's IP MegaStore™ web site at http://www.altera.com/ipmegastore .
About the Atlantic Interface
Supported by Altera and participating Altera Megafunction Partner Program (AMPPSM ) partners, the Atlantic interface is a scalable, high-speed on-chip interface for packet and cell transfer, and provides a synchronous point-to-point connection with flow control. Atlantic interface-compliant functions feature fixed start-of-packet (SOP) alignment to the most significant byte-lane. This alignment significantly eases subsequent packet processing and provides for the direct interconnect of Atlantic interface-compliant functions.
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com .