Sheffield, England - 16 December 2014 - sureCore Ltd. today appointed respected industry veteran Guillaume d'Eyssautier Executive Chairman. sureCore is a leading edge, low-power SRAM IP company focused on advanced technology nodes.
"Guillaume is an incredibly well connected, knowledgeable and experienced executive. Having him as part of sureCore provides a tremendous boost for the company," said Paul Wells, sureCore's CEO.
Mr. d'Eyssautier's appointment comes on the heels of two other important developments. Earlier in the month sureCore closed on a £1m series-A funding round and in March, the company demonstrated 50% power savings on 28nm test chips.
"Guillaume's appointment is the last piece in the jigsaw we needed to drive the company forward and to have a substantial impact on the semiconductor industry," Wells explained.
Mr. d'Eyssautier, added, "I am really excited by this opportunity. sureCore's innovative power saving SRAM IP impacts many aspects of next-generation electronics, where low power consumption is critical."
sureCore's low power SRAM IP technology is particularly attractive to wearable electronics and Internet of Things (IoT) applications where extending battery life is crucial. It is also valuable in the networking space where power and heat dissipation are critical considerations.
"As products become increasingly intelligent, demand for on-chip code memory increases dramatically. The ability to cut embedded SRAM power consumption by up to 50% means a significant reduction in both the thermal and power budgets and that's where sureCore will play a significant role," d'Eyssautier said.
Guillaume d'Eyssautier has held senior level positions in the electronics industry for over 20 years, including CEO of DelfMEMS, CEO of ADD Semiconductor, CEO of picoChip, and VP roles at IBM, Rockwell and Cadence Design Systems. He serves on the European GSA leadership council.
sureCore Limited is an SRAM IP company based in Sheffield, UK, developing low power memories for next generation silicon process technologies. Its world-leading, low power SRAM design is process independent and variability tolerant, making it suitable for a wide range of technology nodes. This IP will help SoC developers meet both challenging power budgets and manufacturability constraints posed by leading edge process nodes.