Henderson, NV – January 29, 2015 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announces the release of ALINT-PRO-CDCTM 2015.01. This latest design verification solution from Aldec enables verification of clock domain crossings and handling of metastability issues in complex, modern multi-clock designs.
“Metastability issues can be easily overlooked during conventional functional verification flow, leading to random design failures in the field,” said Pavlo Leshtaiev, Product Manager, Aldec Software Division. “Having a specialized verification tool is a must for the modern ASIC/FPGA designer to achieve high performance and quality. ALINT-PRO-CDC uncovers critical problems during the RTL Design and Functional Verification stages, significantly cutting down time to market.”
ALINT-PRO-CDC offers a verification strategy comprised of three key elements: Static Structural Verification, Design Constraints Setup, and Dynamic Functional Verification.
Availability
ALINT-PRO-CDC 2015.01 is available today. For additional information or to request a free evaluation download, visit www.aldec.com/Products/ALINT-PRO-CDC.
About Aldec
Aldec Inc., established in 1984 and headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com