Freescale, Cisco, Ciena Give Nod to FD-SOI

Junko Yoshida, EETimes
3/1/2015 06:35 PM EST

SAN FRANCISCO, Calif. and NUREMBERG, Germany — Freescale, Cisco and Ciena have defied the general skepticism of fully-depleted silicon-on-insulator (FD-SOI) by revealing their own experience with the process technology, creating expectations that more companies might follow.

Freescale Semiconductor last week during the Embedded World conference in Nuremberg, Germany, acknowledged that it’s designing chips with FD-SOI process technology.

Geoff Lees, Freescale’s senior vice president and general manager responsible for microcontrollers, told EE Times the company’s plan to use 28nm FD-SOI for its next generation microprocessor iMX7.

A principle engineer at Cisco Systems, last Friday (Feb. 27), also discussed Cisco’s experience with FD-SOI process technology in a panel at the FD-SOI workshop in San Francisco.

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